CDP1883 Intersil Corporation, CDP1883 Datasheet

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CDP1883

Manufacturer Part Number
CDP1883
Description
CMOS 7-Bit Latch and Decoder Memory Interfaces
Manufacturer
Intersil Corporation
Datasheet
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Performs Memory Address Latch and Decoder Func-
• Interfaces Directly with the CDP1800-Series Micropro-
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
Pinout
CDP1883CE CDP1883E
tions Multiplexed or Non-Multiplexed
cessors
5V
10V
-40
RANGE
TEMP.
|
+85
Copyright
o
C to
o
C
©
PDIP
PACKAGE
Intersil Corporation 1999
CLOCK
MA0
MA1
MA2
MA3
MA4
MA5
MA6
V
CE
SS
E20.3
CDP1883, CDP1883C
10
1
2
3
4
5
6
7
8
9
PKG.
NO.
TOP VIEW
(PDIP)
4-129
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multi-
plexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to V
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series micropro-
cessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operat-
ing voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dual-
in-line plastic packages (E Suffix).
20
19
18
17
16
15
14
13
12
11
V
A8
A9
A10
A11
A12
CS0
CS1
CS2
CS3
and Decoder Memory Interfaces
DD
CDP1883C
CDP1883,
CMOS 7-Bit Latch
File Number
1507.2
DD
,

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CDP1883 Summary of contents

Page 1

... The CDP1883 and CDP1883C are functionally identical. They differ in that the CDP1883 has a recommended operat- ing voltage range 10.5V and the C version has a recommended operating voltage range 6.5V. The CDP1883 and CDP1883C are supplied in 20 lead dual- in-line plastic packages (E Suffix). CDP1883, CDP1883C (PDIP) ...

Page 2

... DD (All Voltages Referenced to V Terminal) SS CDP1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1883C -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0. Input Current, Any One Input CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifi ...

Page 3

... Operating current measured at 200kHz for V Functional Diagram MA0 2 MA1 3 MA2 4 MA3 5 MA4 6 MA5 7 MA6 8 CLOCK CDP1883, CDP1883C - + Except as Noted: (Continued CONDITIONS CDP1883 V V (NOTE (V) (V) MIN TYP ...

Page 4

... CDP1800-series microprocessor systems. These microprocessors feature a multiplexed address bus and provide an address latch signal (TPA) that is used as the clock input of the CDP1883. See Figure 2 and Figure 3. This signal is used to latch 7 bits of the high-order address. The lower five high-order address inputs are latched and held to be used with the eight lower-order address inputs to access 8-bit memory ...

Page 5

... MACS MAA VALID CHIP ENABLE t CECS t MACL t CLMA t t CLCS MACS t CLA FIGURE 1. CDP1883 TIMING WAVEFORMS 4-133 = 0 0 100pF CDP1883C (NOTE 1) (NOTE 2) MAX MIN TYP MAX UNITS 175 - 100 175 125 - - - 175 - 100 ...

Page 6

... WAIT TPA CDP1800 CLR SERIES CPU MRD MWR FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH 8-BIT MEMORY CDP1883 LATCH/ DECODER CS3 CLK CS2 CS1 CE CS0 MA0 - MA6 A8 - A12 WAIT CLR A8 - A12 TPA ADDRESS BUS CDP1800 CDM5364 SERIES ...

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