W27E020-12 Winbond, W27E020-12 Datasheet

no-image

W27E020-12

Manufacturer Part Number
W27E020-12
Description
256K X 8 ELECTRICALLY ERASABLE EPROM
Manufacturer
Winbond
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W27E020-12
Manufacturer:
AD
Quantity:
4
GENERAL DESCRIPTION
The W27E020 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 262144
provides an electrical chip erase function.
FEATURES
PIN CONFIGURATIONS
High speed access time:
70/90/120 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 1 mA (max.)
Single 5V power supply
Q0
A6
A5
A4
A3
A2
A1
A0
A7
GND
A12
Vpp
A15
A16
Q0
Q2
A1
A0
Q1
A7
A6
A5
A4
A3
A2
256K
5
10
11
12
13
6
7
8
9
1
4
Q
1
A
1
2
4 3 2 1 3
1
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
A
1
5
32-pin PLCC
1
5
Q
2
A
1
6
1
6
G
N
D
V
p
p
1
7
Q
3
1
8
V
c
c
2
Q
4
8 ELECTRICALLY ERASABLE EPROM
/
P
G
M
1
9
Q
5
3
1
21
32
31
30
29
28
27
26
25
24
23
22
19
17
20
18
A
1
7
2
0
Q
6
3
0
28
25
24
22
21
29
27
26
23
8 bits that operates on a single 5 volt power supply. The W27E020
A10
PGM
A17
A14
A13
A8
A9
A11
OE
CE
Q7
Q6
Q5
Q4
Q3
Vcc
CE
Q7
A14
A13
A8
A9
A11
OE
A10
- 1 -
BLOCK DIAGRAM
PIN DESCRIPTION
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 32-pin 600 mil DIP and
PLCC
SYMBOL
A0 A17
Q0 Q7
PGM
GND
V
V
OE
CE
PGM
CC
PP
CE
OE
GND
A0
A17
.
V
V
CC
PP
Publication Release Date: December 1997
Preliminary W27E020
DECODER
CONTROL
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
DESCRIPTION
OUTPUT
BUFFER
ARRAY
CORE
Revision A1
Q0
Q7
.

Related parts for W27E020-12

W27E020-12 Summary of contents

Page 1

... ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27E020 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 provides an electrical chip erase function. FEATURES High speed access time: 70/90/120 nS (max.) Read operating current (max.) Erase/Programming operating current (max ...

Page 2

... The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E020 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. ...

Page 3

... OE and PGM. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27E020 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur ...

Page 4

... IL, IH, PGM = 2 -0 and removed simultaneously or after Preliminary W27E020 RATING UNIT -55 to +125 -65 to +125 -0 +0 -0.5 to +14.5 -0.5 to +14.5 LIMITS MIN. TYP. MAX. - -0.3 - 0.8 2 0.45 2 13.75 14.0 14.25 13.75 14 ...

Page 5

... Jig and Scope for 70 nS (Including Jig and Scope) Test Points 2.4V 2.0V 2.0V 0.8V 0.8V 0.45V Test Point 3.0V 1.5V 1.5V 0V Publication Release Date: December 1997 - 5 - Preliminary W27E020 MAX. UNIT CONDITIONS 90/120 nS 0.45V to 2. 0.8V/2. 100 pF -0.4 mA/2 ...

Page 6

... and removed simultaneously or after Preliminary W27E020 LIMITS MIN. TYP. MAX - 1 100 - - -0.3 - 0 0. W27E020-12 MAX. MIN. MAX 120 - - 90 - 120 - 90 - 120 - UNIT UNIT ...

Page 7

... PGM Erase Pulse Width Data Hold Time OE Setup Time Data Valid from OE OE High to Output High Z Address Hold Time after PGM High Address Hold Time (Erase) CE Setup Time Note: V must be applied simultaneously or before V CC Preliminary W27E020 SYM. CONDITIONS ...

Page 8

... Others AHC T DFP Data All One OUT VPS T T OES OE T OEV T PWE T CES - 8 - Preliminary W27E020 Valid Output High Z Blank Check Read Verify Address Address Stable Stable T ACC D D OUT OUT ...

Page 9

... PGM V IL Program Program Verify Address Stable Address Stable T DFP D D Data In Stable OUT OUT CES T OES T OEV T PWP - 9 - Preliminary W27E020 Read Verify Address Valid T ACC D OUT Publication Release Date: December 1997 Revision A1 ...

Page 10

... Address = First Location Vcc = 5V Vpp = 12V Program One 100 S Pulse Increment X Yes X = 25? No Fail Verify One Byte Pass No Last Address? Yes Vcc = 5V Vpp = 5V Compare Fail All Bytes to Original Data Pass Pass Device - 10 - Preliminary W27E020 Fail Verify One Byte Pass Fail Device ...

Page 11

... Vpp = 14V A9 = 14V Chip Erase 100 mS Pulse Address = First Location Increment X Fail Erase Verify Pass No Last Address? Yes Vcc = 5V Vpp = 5V Compare Fail All Bytes to FFs (HEX) Pass Pass Device - 11 - Preliminary W27E020 20? Yes Fail Device Publication Release Date: December 1997 Revision A1 ...

Page 12

... ORDERING INFORMATION PART NO. ACCESS TIME (nS) W27E020-70 70 W27E020-90 90 W27E020-12 120 W27E020P-70 70 W27E020P-90 90 W27E020P-12 120 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...

Page 13

... 32-Lead PLCC Seating Plane Preliminary W27E020 Base Plane Seating Plane Publication Release Date: December 1997 - 13 - Dimension in Inches Dimension in mm Symbol Min ...

Page 14

... Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Preliminary W27E020 PAGE DESCRIPTION Initial Issued Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Memory Lab. ...

Related keywords