W39L040 Winbond, W39L040 Datasheet

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W39L040

Manufacturer Part Number
W39L040
Description
512 K X 8 CMOS FLASH MEMORY
Manufacturer
Winbond
Datasheet

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1. GENERAL DESCRIPTION
The W39L040 is a 4Mbit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For flexible
erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0.
The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt
V
operations with extremely low current consumption (compared to other comparable 3.3-volt flash
memory products). The device can also be programmed and erased by using standard EPROM
programmers.
2. FEATURES
PP
Fast Erase operation:
− Chip Erase cycle time: 100 mS (max.)
− Sector Erase cycle time: 25 mS (max.)
− Page Erase cycle time: 25 mS (max.)
8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
Single 3.3-volt operations
− 3.3-volt Read
− 3.3-volt Erase
− 3.3-volt Program
Fast Program operation:
− Byte-by-Byte programming: 50 µS (max.)
Read access time: 70/90 nS
Any individual sector or page can be erased
is not required. The unique cell architecture of the W39L040 results in fast program/erase
512K × 8 CMOS FLASH MEMORY
- 1 -
Available packages: 32L PLCC, 32L TSOP (8 x
20 mm) and 32L STSOP (8 x 14 mm)
Hardware protection:
− Optional 16K byte or 64K byte Top/Bottom
Flexible 4K-page size can be used as
Parameter Blocks
Typical program/erase cycles: 1K/10K
Twenty-year data retention
Low power consumption
− Active current: 10 mA (typ.)
− Standby current: 2 µA (typ.)
End of program detection
− Software method: Toggle bit/Data polling
TTL compatible I/O
JEDEC standard byte-wide pinouts
Boot Block with lockout protection
Publication Release Date: February 10, 2003
W39L040
Revision A3

Related parts for W39L040

W39L040 Summary of contents

Page 1

... GENERAL DESCRIPTION The W39L040 is a 4Mbit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. ...

Page 2

... A0 − A18 DQ2 23 DQ1 22 DQ0 21 DQ0 − DQ7 # #OE # W39L040 OUTPUT CONTROL BUFFER A0 CORE . DECODER ARRAY . A18 PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply DD Ground ...

Page 3

... Device Bus Operation Read Mode The read operation of the W39L040 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins ...

Page 4

... The manufacturer and device codes may also be read via the command register, for instance, when the W39L040 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Auto-select Codes". Byte 0 ( represents the manufacturer′s code (Winbond = DAH) and byte 1 ( device identifier code (W39L040 = B6hex) ...

Page 5

... The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L040 = B6hex). To terminate the operation necessary to write the auto-select exit command sequence into the register ...

Page 6

... DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors/pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations W39L040 ...

Page 7

... Erase Algorithm, or sector erase time-out (see "Command Definitions"). DQ6: Toggle Bit The W39L040 also features the "Toggle Bit" method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero ...

Page 8

... ID MODE Read Write Standby Write Inhibit Output Disable Auto select Manufacturers ID Auto select Device ID Auto-select Codes (High Voltage Method ±0.5V DESCRIPTION Manufacturer ID: Winbond Device ID: W39L040 Sector Address Table A18 A17 SECTOR SA0 0 0 SA1 0 0 SA2 0 1 SA3 0 1 ...

Page 9

... PA = 1FXXXh to 10xxx for Page 15 to page 0 in Sector1 (Please reference to left column 0FXXXh to 00xxx for Page 15 to page 0 in Sector0 (Please reference to left column) Publication Release Date: February 10, 2003 - 9 - W39L040 5TH CYCLE 6TH CYCLE 7TH CYCLE Addr. Data Addr. Data Addr. Data ...

Page 10

... Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 10 - W39L040 Pause T BP ...

Page 11

... Start (see below) Pause T Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Sector Address/30H Publication Release Date: February 10, 2003 - 11 - W39L040 / SEC PEC Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Page Address/50H ...

Page 12

... DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 12 - W39L040 = Any of the sector addresses within the sector being erased during sector erase operation = Any of the page addresses within the page being erased during page erase operation = Any of the device addresses being erased ...

Page 13

... Load data 55 to address 2AAA Load data 40/ lock 64K Boot Block lcok 16K Boot Block address 5555 Load data XX 7FFFF(XX) to lock Top Boot Block to 000000(XX) to lock Bottom Boot Block address 7FFFF/0 Pause 2 mS Publication Release Date: February 10, 2003 - 13 - W39L040 Exit Revision A3 ...

Page 14

... Read address = 0001 data = B6 (4) Read address=02/7FFF2 for Bottom/Top data:in DQ0="1" or "0" for 64K Boot Block or DQ1="1" or "0" for 16K Boot Block - 14 - W39L040 Load data AA to address 5555 Load data 55 to address 2AAA Load data F0 to address 5555 µ ...

Page 15

... OUT 2 -0 SYMBOL CONDITIONS OUT OUT Publication Release Date: February 10, 2003 - 15 - W39L040 RATING UNIT -2.0 to +4.6 V ° +70 °C -40 to +85 °C -65 to +125 -2.0 to +4.6 V -2.0 to +13.0 V LIMITS UNIT MIN. TYP. MAX µ ...

Page 16

... AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load AC Test Load and Waveform <5 nS 1.5V/1.5V 1 TTL Gate and C +3.3V D OUT 30 pF (Including Jig and Scope) Input Output 3V 1.5V 1.5V 0V Test Point Test Point - 16 - W39L040 CONDITIONS = Ω 1.2K Ω 2.1K ...

Page 17

... T 0 OEH T 100 CP T 100 WP T 100 WPH and (b) low level signal's reference level Publication Release Date: February 10, 2003 - 17 - W39L040 W39L040-90 UNIT MIN. MAX TYP. ...

Page 18

... Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay SYMBOL T . READ WRITE PU W39L040-70 SYM. MIN. MAX OEP CEP OET CET - 18 - W39L040 TYPICAL UNIT µS 100 5 mS W39L040-90 UNIT MIN. MAX ...

Page 19

... Controlled Command Write Cycle Timing Diagram Address A18-0 #CE #OE #WE DQ7 OLZ T CLZ T OH Data Valid OES Data Valid Publication Release Date: February 10, 2003 - 19 - W39L040 T OHZ T CHZ High-Z Data Valid OEH T WPH T DH Revision A3 ...

Page 20

... SB0 OES High Z Six-byte code for 3.3V-only software chip erase 5555 5555 2AAA WPH SB2 SB3 SB1 - 20 - W39L040 T CPH CP T OEH T DS Data Valid T DH 2AAA 5555 Internal Erase starts SB4 SB5 ...

Page 21

... DQ7 Six-byte commands for 3.3V-only Sector/Page Erase 5555 5555 2AAA WPH SB2 SB3 SB1 CEP T OEH T OEP Publication Release Date: February 10, 2003 - 21 - W39L040 2AAA SA/PA 55 30/ Internal Erase starts SB4 SB5 OES X X Revision A3 ...

Page 22

... Timing Waveforms, continued Toggle Bit Timing Diagram Address A18-0 #WE #CE #OE DQ6 T OEH W39L040 T OES ...

Page 23

... W39L040T-90B 90 W39L040Q-70B 70 W39L040Q-90B 90 W39L040P-70J 70 W39L040P-90J 90 W39L040T-70J 70 W39L040T-90J 90 W39L040Q-70J 70 W39L040Q-90J 90 W39L040P-70K 70 W39L040P-90K 90 W39L040T-70K 70 W39L040T-90K 90 W39L040Q-70K 70 W39L040Q-90K 90 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...

Page 24

... HOW TO READ THE TOP MARKING Example: The top marking of 32-pin TSOP W39L040T-70 W39L040T-70 2138977A-A12 149OBSA st 1 line: Winbond logo nd 2 line: the part number: W39L040T- line: the lot number th 4 line: the tracking code: 149 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ... etc revision ...

Page 25

... Publication Release Date: February 10, 2003 - 25 - W39L040 Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.140 3.56 A 0.020 0. 0.105 0.110 0.115 2.67 2.80 2. 0.026 0.032 0.66 0.81 ...

Page 26

... Symbol Min 0.002 A 2 0.035 b 0.007 E c 0.004 0.020 0.000 θ W39L040 Dimension in mm Nom. Max. Min. Nom. Max. 0.047 1.20 0.006 0.05 0.15 0.95 0.040 0.041 1.00 1.05 0.17 0.009 0.010 0.22 0.27 0.10 ----- 0.008 ----- 0.21 0.488 12.40 0.315 8.00 0.551 14.00 0.020 0.50 0.50 0.70 0.024 ...

Page 27

... Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Publication Release Date: February 10, 2003 - 27 - W39L040 DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...

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