M3488 ST Microelectronics, M3488 Datasheet

no-image

M3488

Manufacturer Part Number
M3488
Description
256 x 256 DIGITAL SWITCHING MATRIX
Manufacturer
ST Microelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3488
Manufacturer:
ST
Quantity:
22
Part Number:
M3488
Manufacturer:
ST
0
Part Number:
M3488B
Manufacturer:
ST
0
Part Number:
M3488B1
Manufacturer:
AVAGO
Quantity:
4 500
Part Number:
M3488B1
Manufacturer:
WSI
Quantity:
780
Part Number:
M3488B1
Manufacturer:
ST
0
Part Number:
M3488B1
Manufacturer:
ST
Quantity:
20 000
Part Number:
M3488BI
Manufacturer:
ST
0
November 1994
.
.
.
.
.
.
.
.
.
.
.
ABSOLUTE MAXIMUM RATINGS
Stresses above those l isted under ” Absolute Maximum Ratings” may cause permanent damage to the devi ce. This is a stress
rati ngs only and functional operation of the device at these or any other conditions above those indicated in the operating con-
ditions of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect devi ce
reliabili ty.
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Symbol
256 INPUT AND 256 OUTPUT CHANNEL
CMOS DIGITAL SWITCHING MATRIX COM-
PATIBLE WITH M088
BUILDING BLOCK DESIGNED FOR LARGE
CAPACITY ELECTRONIC EXCHANGES, SUB-
SYSTEMS AND PABX
NO EXTRA PIN NEEDED FOR NOT-BLOCK-
ING SINGLE STAGE AND HIGHER CAPACITY
SYNTHESIS BLOCKS (512 or 1024 channels)
EUROPEAN TELEPHONE STANDARD COM-
PATIBLE (32 serial channels per frame)
PCM INPUTS AND OUTPUTS MUTUALLY
COMPATIBLE
ACTUAL INPUT-OUTPUT CHANNEL CON-
NECTIONS STORED AND MODIFIED VIA AN
ON CHIP 8-BIT PARALLEL MICROPROCES-
SOR INTERFACE
TYPICAL BIT RATE : 2Mbit/s
TYPICAL SYNCHRONIZATION RATE : 8KHz
(time frame is 125 s)
5V P0WER SUPPLY
CMOS & TTL INPUT/OUTPUT LEVELS COM-
PATIBLE
HIGH DENSITY ADVANCED 1.2 m HCMOS3
PROCESS
V
P
T
T
V
V
I
CC
O
stg
tot
op
O
I
Supply Voltage
Input Voltage
Off State Output Voltage
Current at Digital Outputs
Total Package Power Dissipation
Storage Temperature Range
Operating Temperature Range
Parameter
256 x 256 DIGITAL SWITCHING MATRIX
Main instructions controlled by the microproc-
.
essor interface
.
.
.
.
.
CHANNEL CONNECTION/DISCONNECTION
OUTPUT CHANNEL DISCONNECTION
INSERTION OF A BYTE ON A PCM OUTPUT
CHANNEL/DISCONNECTION
TRANSFER TO THE MICROPROCESSOR OF
A SINGLE PCM OUTPUT CHANNEL SAMPLE
TRANSFER TO THE MICROPROCESSOR OF
A SINGLE OUTPUT CHANNEL CONTROL
WORD
TRANSFER TO THE MICROPROCESSOR OF
A SELECTED 0 CHANNEL PCM INPUT DATA
M3488B1
DIP40
ORDERING NUMBERS:
Test Conditions
-0.3 to V
-0.3 to V
-65 to 150
-0.3 to 7
0 to 70
1.5
30
PREL IMINARY DATA
CC
CC
PQFP44
+0.3
+0.3
M3488Q1
M3488
Unit
mA
W
V
V
V
C
C
1/18

Related parts for M3488

M3488 Summary of contents

Page 1

... TRANSFER TO THE MICROPROCESSOR SINGLE PCM OUTPUT CHANNEL SAMPLE TRANSFER TO THE MICROPROCESSOR OF A SINGLE OUTPUT CHANNEL CONTROL . WORD TRANSFER TO THE MICROPROCESSOR OF A SELECTED 0 CHANNEL PCM INPUT DATA Parameter M3488 PREL IMINARY DATA PQFP44 M3488Q1 Test Conditions Unit - ...

Page 2

... M3488 PIN CONNECTIONS (Top views) DIP40 EXCHANGE NETWORKS APPLICATIONS 256 PCM links network (160 or 192 DSM) : the link module shown on the next page. 2048 PCM links network (1792 or 2048 DSM) : the 256 x 256 link network is shown above. 2/ ...

Page 3

... EXCHANGE NETWORKS APPLICATIONS (continued) Single Stage/Sixteen Devices Configuration ( links or 1024 channels). M3488 3/18 ...

Page 4

... M3488 BLOCK DIAGRAM 4/18 ...

Page 5

... applied; Pins 35 CC and 36 tied after Device Initialization 16 Clock Freq. = 4.096MHz M3488 Value Unit 4. 5.25 V 4.096 MHz 8 KHz Min. Typ. Max. Unit 5 ...

Page 6

... M3488 A.C. ELECTRICAL CHARACTERISTICS (T All A.C. characteristics are valid 250 s after V Signal Symbol Parameter CK (clock) t Clock Period CK t Clock Low Level Width WL t Clock High Level Width WH t Rise Time R t Fall Time F SYNC t Low Level Setup Time SL (frame pulse) t Low Level Hold Time ...

Page 7

... Inactive Case 0 Active Case 0 Active Case 0 Inactive Case 0 Inactive Case 0 130 130 Instructions 5 and 6 Instruction 4 150pF 130 200pF 200pF L M3488 Max. Unit 2 7 120 7/18 ...

Page 8

... M3488 PCM TIMING, RESET, SYNC WRITE OPERATION TIMING 8/18 ...

Page 9

... READ OPERATION TIMING GENERAL DESCRIPTION The M3488 is intendedfor large telephoneswitching systems, mainly central exchanges, digital line con- centrators and private branch exchanges where a distributed microcomputer control approach is ex- tensively used. It consists of a speech memory (SM), a control memory (CM), a serial/parallel and a parallel/serial converter, an internal parallel bus, an interface (8 data lines, 11 control signals) and dedicated control logic ...

Page 10

... M3488 PINS FUNCTION Symbol Data bus C/D Input control A1, S1, A2, S2 Address select or match CS1, CS2 Chip select WR Data transfer enable RD Read enable DR Data ready RESET RESET control CLOCK Input master clock SYNC Input synchronization IN PCM PCM input bus OUT PCM 7 ...

Page 11

... PCM output channels are also set to high impedance state. CLOCK Input master clock. Typical frequency is 4.096MHz. First division gives an internal clock controlling the input and output channels bit rate. SYNC Input synchronization signal is active low. Typical frequency is 8kHz. M3488 nsec WL(CK) 11/18 ...

Page 12

... M3488 Internal time bases are forced by synchronism to an assigned count number in order to restore channels and bit sequential addressing to a known state. Count difference between the bases is 32, corre- spondingto two time slots, that is the minimum PCM propagation time, or latency time. INP PCM 7 to INP PCM 0 PCM input busses or pins ...

Page 13

... Bi0 Ci4 Ci3 Ci2 Ci1 Ci0) for match condition OR2: that is Bo0 for mismatch condition Bo0 for match condition M3488 for sequence OR2 - OR1 and for sequenceOR1 - OR2. More Notes 13/18 ...

Page 14

... M3488 INSTRUCTION2: OUTPUT CHANNEL DISCONNECTION Control Signals Match C Yes Yes Yes (Bo2 Bo1 INSTRUCTION3: LOADING ON A PCM OUTPUT CHANNEL FROM A MICROPROCESSOR BYTE Control Signals ...

Page 15

... OR2: see below. SYNC and the first clock (CK) bit contained in the slot time for bit 0 of channel 0. In order to use M3488 with these frames suffi- cient, using the data bytes sent by the microproces- sor, to modify the numbering of a few channels. ...

Page 16

... M3488 PQFP44 (10 x 10) PACKAGE MECHANICAL DATA DIM. MIN. TYP 0.25 A2 1.95 2.00 B 0.30 c 0.13 D 12.95 13.20 D1 9.90 10.00 D3 8.00 e 0.80 E 12.95 13.20 E1 9.90 10.00 E3 8.00 L 0.65 0. 16/18 mm MAX. MIN. 2.45 0.010 2.10 0.077 0.45 0.012 0.23 0.005 13.45 0.51 10.10 0.390 13.45 0.510 10.10 0.390 0.95 0.026 0 (min.), 7 (max PQFP44 inch TYP. MAX. 0.096 0.079 ...

Page 17

... DIP40 PACKAGE MECHANICAL DATA DIM. MIN TYP a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 48. 4.445 L mm MAX MIN 0.31 0.009 52.58 16.68 0.598 14.1 3.3 M3488 inch TYP MAX 0.025 0.018 0.012 0.050 2.070 0.657 0.100 1.900 0.555 0.175 0.130 17/18 ...

Page 18

... M3488 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice ...

Related keywords