LA-ISPPAC-POWR1014 LATTICE [Lattice Semiconductor], LA-ISPPAC-POWR1014 Datasheet
LA-ISPPAC-POWR1014
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LA-ISPPAC-POWR1014 Summary of contents
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... ADC* 4 Digital 4 Timers LA-ispPAC-POWR1014A *LA-ispPAC-POWR1014A only. Description Lattice’s Power Manager II LA-ispPAC-POWR1014 general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E LA-ispPAC-POWR1014/A device provides 10 indepen- dent analog input channels to monitor power supply test points ...
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... FETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The LA-ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD ...
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... Open Drain Output 1 OUT14 Open Drain Output 8 40 RESETb Digital I/O 42 PLDCLK Digital Output LA-ispPAC-POWR1014/A Automotive Family Data Sheet Voltage Range 1, 2 VCCINP PLD Logic Input 1 Registered by MCLK 1, 3 VCCINP PLD Logic Input 2 Registered by MCLK 1, 3 VCCINP PLD Logic Input 3 Registered by MCLK ...
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... VCCD and VCCA pins must be connected together on the circuit board. 7. Open-drain outputs require an external pull-up resistor to a supply. 8. The RESETb pin should only be used for cascading two or more LA-ispPAC-POWR1014/A devices. 9. These pins should be connected to GNDD (LA-ispPAC-POWR1014 device only). LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... CCINP CCINP I JTAG supply current CCJ I Core and analog supply current CCPROG 1. Includes currents on V and V CCD CCA LA-ispPAC-POWR1014/A Automotive Family Data Sheet Parameter Conditions HVOUT[1:2] OUT[3:14] Conditions 2 During E programming pins OUT[3:14] pins HVOUT[1:2] pins in open-drain mode Power applied ...
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... Gate driver output voltage PP Gate driver source current I OUTSRC (HIGH state) Gate driver sink current I OUTSINK (LOW state) LA-ispPAC-POWR1014/A Automotive Family Data Sheet Conditions 1 range, operating temperature, process. CCA Conditions 8V setting 6V setting Four settings in software FAST OFF mode Controlled ramp settings 5-6 Min ...
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... Threshold above which RESETb is HIGH TH V Threshold above which RESETb is valid T Capacitive load on RESETb for master/slave C L operation 1. Corresponds to VCCA and VCCD supply voltages. LA-ispPAC-POWR1014/A Automotive Family Data Sheet Conditions 2 Time from I C request Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 3 pin (theoretical maximum is 6 ...
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... Lattice Semiconductor Figure 5-2. LA-ispPAC-POWR1014/A Power-On Reset Reset State LA-ispPAC-POWR1014/A Automotive Family Data Sheet T BRO T T RST POR Start Up State T START Analog Calibration T GOOD 5-8 VCC RESETb MCLK PLDCLK AGOOD (Internal) ...
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... PLDCLK output frequency PLDCLK Timers Range of programmable Timeout Range timers (128 steps) Spacing between available Resolution adjacent timer intervals Accuracy Timer accuracy LA-ispPAC-POWR1014/A Automotive Family Data Sheet Over Recommended Operating Conditions Conditions f = 8MHz CLK f = 8MHz CLK f = 8MHz CLK 5-9 Min. ...
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... IN[1:4] referenced TDO, TDI, TMS, ATDI, TDISEL referenced to V CCINP 2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded. LA-ispPAC-POWR1014/A Automotive Family Data Sheet Over Recommended Operating Conditions Conditions HVOUT[1:2] in open drain mode and pulled ...
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... CONVERT readout. When F is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit. I2C LA-ispPAC-POWR1014/A Automotive Family Data Sheet 1 Definition 5-11 100KHz 400KHz Min ...
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... VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 5-4. Programming Timing Diagram VIH TMS VIL SU1 H t CKH VIH TCK VIL State Update-IR LA-ispPAC-POWR1014/A Automotive Family Data Sheet Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL ...
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... Theory of Operation Analog Monitor Inputs The LA-ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 5-7. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV ‘ ...
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... Lattice Semiconductor Figure 5-7. LA-ispPAC-POWR1014/A Voltage Monitors VMONx Trip Point A Trip Point B Analog Input Figure 5-7 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. ...
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... To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. LA-ispPAC-POWR1014/A Automotive Family Data Sheet UTP LTP ...
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... Low-V Sense LA-ispPAC-POWR1014/A Automotive Family Data Sheet Coarse Range Setting 1.360 1.612 1.923 2.290 1.353 1.603 1.913 2.278 1.346 1.595 1.903 2.266 1.338 1.586 1.893 2 ...
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... Low-V Sense LA-ispPAC-POWR1014/A Automotive Family Data Sheet 1.346 1.595 1.903 2.266 1.338 1.586 1.893 2.254 1.331 1.578 1.883 2.242 1.324 1.570 1.873 2.230 1.317 1 ...
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... The third section in the LA-ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the com- parator output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the fi ...
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... Lattice Semiconductor VMON Voltage Measurement with the On-chip Analog to Digital Converter (ADC, LA-ispPAC-POWR1014A Only) The LA-ispPAC-POWR1014A has an on-chip analog to digital converter that can be used for measuring the volt- ages at the VMON inputs. Figure 5-9. ADC Monitoring VMON1 to VMON10 VMON1 VMON2 VMON3 Programmable Analog ...
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... GLB1, GLB2, and GLB3. Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the LA-ispPAC-POWR1014/A device. The output signals of the LA-ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 5-10. GLB3 generates timer control ...
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... PT0 Polarity Clock Clock and Timer Functions Figure 5-12 shows a block diagram of the LA-ispPAC-POWR1014/A’s internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 5-12. Clock and Timer System Internal Oscillator 8MHz The internal oscillator runs at a fi ...
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... In addition to being usable as digital open-drain outputs, the LA-ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output pins can be programmed to operate as high-voltage FET drivers. Figure 5-14 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the PLD, or with the LA-ispPAC-POWR1014A, from the I bus (see Figure 5-14). For further details on controlling the outputs through I face section of this data sheet ...
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... CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the LA-isp- PAC-POWR1014/A device operation, results in the device aborting all operations and returning to the power-on reset state. The status of the power supplies which are being enabled by the LA-ispPAC-POWR1014/A will be determined by the state of the outputs shown above. ...
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... Each slave device on a given I C bus is assigned a unique address. The LA-ispPAC-POWR1014A implements the 7-bit addressing portion of the standard. Any 7-bit address can be assigned to the LA-ispPAC-POWR1014A device by programming through JTAG. When selecting a device address, one should note that several addresses are ...
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... The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the LA-ispPAC-POWR1014A asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the LA-ispPAC-POWR1014A. ...
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... VMON_STATUS2 (Read Only also possible to directly read the value of the voltage present on any of the VMON inputs by using the LA-isp- PAC-POWR1014A’s ADC. Three registers provide the I LA-ispPAC-POWR1014/A Automotive Family Data Sheet Description R VMON input status Vmon[4:1] R VMON input status Vmon[8:5] R ...
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... When the conversion is complete, the result may be read out of the ADC by 2 performing two I C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH recom- 2 mended that the I C master load a second conversion command only after the completion of the current conversion LA-ispPAC-POWR1014/A Automotive Family Data Sheet ...
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... Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to drive the pin, and does not sample the actual level present on the output pin. For example output is set high LA-ispPAC-POWR1014/A Automotive Family Data Sheet note in specifications), the only way to insure a valid ADC ...
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... OUTPUT_STATUS1 (Read Only 0x0E - GP_OUTPUT1 (Read/Write) GP8 GP7 b7 b6 0x0F - GP_OUTPUT2 (Read/Write The UES word may also be read through the I LA-ispPAC-POWR1014/A Automotive Family Data Sheet Configuration MUX 14 14 Output_Status0 Output_Status1 Interface Unit OUT6 ...
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... The I C interface also provides the ability to initiate reset operations. The LA-ispPAC-POWR1014A may be reset by issuing a write of any value to the I is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I section of this data sheet for further information. ...
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... After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the LA-ispPAC-POWR1014A. As part of the service func- tions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP3_ENb to re-enable the SMBAlert function ...
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... Circuit designs are entered graphically and then verified, all within the PAC-Designer environ- ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the LA-ispPAC-POWR1014/A. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading. ...
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... JTAG signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the LA-ispPAC-POWR1014/A are connected to the header as shown in Figure 5-27. Note: The LA-ispPAC-POWR1014/A should be the last device in the JTAG chain. ...
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... VCCD and VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the LA-ispPAC-POWR1014/A is using the VCCPROG pin, its VCCD and VCCA pins can be open or pulled low. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOS- FET driver are driven low, and all other inputs are ignored ...
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... IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the LA-ispPAC-POWR1014/A is facilitated via an IEEE 1149.1 test access port (TAP used by the LA-ispPAC-POWR1014 serial programming interface. A brief description of the LA-ispPAC-POWR1014/A JTAG interface follows. For complete details of the reference specifica- tion, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149 ...
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... E CMOS cells these non-volatile cells that store the configuration or the LA-ispPAC-POWR1014/A. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibil- ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func- tionally specifi ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The LA-ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured ...
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... POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The LA-ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 5-11 ...
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... Lattice Semiconductor LA-ispPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specifica- tion compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000). The optional IDCODE (identification code) instruction is incorporated in the LA-ispPAC-POWR1014/A and leaves it in its functional mode when executed. It selects the Device Identifi ...
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... PROGRAM_DISABLE – This instruction disables the programming mode of the LA-ispPAC-POWR1014/A. The Test-Logic-Reset JTAG state can also be used to cancel the programming mode of the LA-ispPAC-POWR1014/A. UES_READ – This instruction both reads the E between the TDI and TDO pins (as shown in Figure 5-30), to support programming or reading of the user electronic signature bits ...
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... The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. ERASE_DONE_BIT – This instruction clears the ‘Done’ bit, which prevents the LA-ispPAC-POWR1014/A sequence from starting. PROGRAM_DONE_BIT – This instruction sets the ‘Done’ bit, which enables the LA-ispPAC-POWR1014/A sequence to start. RESET – ...
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... THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. LA-ispPAC-POWR1014/A Automotive Family Data Sheet 0. SEATING PLANE ...
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... LA-ispPAC-POWR1014/A Ordering Information Lead-Free Packaging Part Number LA-ispPAC-POWR1014A-01TN48E LA-ispPAC-POWR1014-01TN48E Package Options OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 LA-ispPAC-POWR1014/A Automotive Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP LA-ispPAC-POWR1014A 6 48-Pin TQFP ...
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... Use of products in such applications is fully at the risk of the customer, subject to applicable laws and regulations governing limitations on product liability. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com LA-ispPAC-POWR1014/A Automotive Family Data Sheet LA-ispPAC-POWR1014 6 ...
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... Lattice Semiconductor Revision History Date Version January 2008 01.0 June 2008 01.1 LA-ispPAC-POWR1014/A Automotive Family Data Sheet Change Summary Initial release. Added timing diagram and timing parameters to "Power-On Reset" specifications. Modified PLD Architecture figure to show input registers. 2 Updated I C Control Registers table. ...