RFPIC12F675 MICROCHIP [Microchip Technology], RFPIC12F675 Datasheet
RFPIC12F675
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RFPIC12F675 Summary of contents
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... Microchip Technology Inc. 20-Pin FLASH-Based 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter Preliminary Data Sheet DS70091A ...
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families ...
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... Community gate and garage door openers • Burglar alarm systems • Building access • Low power telemetry TM ) • Meter reading • Tire pressure sensors • Wireless sensors DD = 3V) Device rfPIC12F675K rfPIC12F675F rfPIC12F675H Preliminary •1 20 GP0/CIN+/ICSPDAT 2 19 GP1/CIN-/ICSPCLK 3 18 GP2/T0CKI/INT/COUT 4 ...
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... Table of Contents 1.0 Device Overview ............................................................................................................................................................................ 3 2.0 Memory Organization..................................................................................................................................................................... 5 3.0 GPIO Port ................................................................................................................................................................................... 17 4.0 Timer0 Module............................................................................................................................................................................ 25 5.0 Timer1 Module with Gate Control ............................................................................................................................................... 28 6.0 Comparator Module .................................................................................................................................................................... 33 7.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 39 8.0 Data EEPROM Memory.............................................................................................................................................................. 45 9.0 UHF ASK/FSK Transmitter ......................................................................................................................................................... 49 10.0 Special Features of the CPU ...................................................................................................................................................... 55 11.0 Instruction Set Summary ............................................................................................................................................................ 73 12.0 Development Support ................................................................................................................................................................. 81 13.0 Electrical Specifications .............................................................................................................................................................. 87 14.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 113 15 ...
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... Data Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The rfPIC12F675 comes in a 20-pin SSOP package. Figure 1-1 shows a block diagram of the rfPIC12F675 device. Table 1-1 shows the pinout description. 8 Data Bus RAM ...
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... General purpose input. Individually controlled interrupt-on- change. No Master Clear Reset — Programming voltage Bias RF Crystal — RF Enable Reference Clock/4 Output (on rfPIC12F675K/F) — Reference Clock/8 Output (on rfPIC12F675H) Bias Power Select — RF Power Supply — RF Ground Reference — RF power amp output to antenna — RF Ground Reference — ...
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... The IRP and RP1 bits STATUS<7:6> are reserved and should always be maintained as ‘0’s. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized the rfPIC12F675 devices. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4). 000h 0004 0005 03FFh ...
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... The Special Function registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS70091A-page 6 FIGURE 2-2: DATA MEMORY MAP OF THE rfPIC12F675 File Address (1) Indirect addr. 00h TMR0 01h ...
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... GPIE T0IF — — CMIF — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — CINV CIS CM2 — — CHS1 CHS0 Preliminary rfPIC12F675 Value on Bit 1 Bit 0 Page POR, BOD 16,63 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx GPIO1 GPIO0 --xx xxxx — ...
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... TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (1) 80h INDF Addressing this Location uses Contents of FSR to Address Data Memory 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter's (PC) Least Significant Byte (2) 83h STATUS IRP RP1 84h FSR ...
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... STATUS bits. For other instructions not affecting any STATUS bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the rfPIC12F675 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. ...
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... OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External GP2/INT interrupt • TMR0 • Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG — OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 GPPU INTEDG bit 7 bit 7 ...
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... T0IF bit. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. rfPIC12F675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...
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... PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ...
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... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. rfPIC12F675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...
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... PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON Register bits are shown in Register 2-6. REGISTER 2-6: PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 — ...
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... Microchip Technology Inc. 2.3.2 STACK The rfPIC12F675 Family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed interrupt causes a branch ...
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... Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results operation (although STATUS bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING rfPIC12F675 Direct Addressing (1) From Opcode RP1 RP0 6 ...
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... TRISIO 3.2 Additional Pin Functions Every GPIO pin on the rfPIC12F675 has an interrupt- on-change option and every GPIO pin, except GP3, has a weak pull-up option. The next two sections describe these functions. 3.2.1 WEAK PULL-UP Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up ...
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... REGISTER 3-2: TRISIO — GPIO TRISTATE REGISTER (ADDRESS: 85h) U-0 — bit 7 bit 7-6: Unimplemented: Read as ’0’ bit 5-0: TRISIO<5:0>: General Purpose I/O Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated GPIO pin configured as an output. Note: TRISIO<3> always reads 1. Legend Readable bit ...
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... Q2 cycle), then the GPIF inter- rupt flag may not get set. U-0 R/W-0 R/W-0 R/W-0 — IOC5 IOC4 IOC3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary rfPIC12F675 R/W-0 R/W-0 R/W-0 IOC2 IOC1 IOC0 bit Bit is unknown DS70091A-page 19 ...
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... Pin Descriptions and Diagrams Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. 3.3.1 GP0/AN0/CIN+ Figure 3-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: • ...
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... Master Clear Reset FIGURE 3-3: Data Bus RD TRISIO PORT Weak IOC RD IOC V DD Interrupt-on-Change I/O pin Preliminary rfPIC12F675 PP BLOCK DIAGRAM OF GP3 MCLRE RESET I/O pin SS V MCLRE PORT DS70091A-page 21 ...
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... GP4/AN3/T1G/OSC2/CLKOUT Figure 3-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D • a TMR1 gate input • a crystal/resonator connection • a clock output FIGURE 3-4: BLOCK DIAGRAM OF GP4 Analog Input Mode ...
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... TRISIO2 TRISIO1 WPU5 WPU4 — WPU2 WPU1 IOC5 IOC4 IOC3 IOC2 IOC1 ADCS1 ADCS0 ANS3 ANS2 ANS1 Preliminary rfPIC12F675 Value on: Value on all Bit 0 POR, other BOD RESETS --xx xxxx --uu uuuu GP0 0000 0000 0000 000u GPIF -0-0 0000 -0-0 0000 CM0 1111 1111 1111 1111 ...
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... NOTES: DS70091A-page 24 Preliminary 2003 Microchip Technology Inc. ...
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... The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut-off during SLEEP. 1 SYNC 2 Cycles 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA Preliminary rfPIC12F675 edge (T0SE) control bit Mid-Range Reference Manual Data Bus 8 TMR0 Set Flag bit T0IF on Overflow WDT Time-out DS70091A-page 25 ...
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... Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... Bit 1 T0IE INTE GPIE T0IF INTF T0CS T0SE PSA PS2 PS1 TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 Preliminary rfPIC12F675 CHANGING PRESCALER (TIMER0→WDT) ;Bank 0 ;Clear WDT ;Clear TMR0 and ; prescaler ;Bank 1 ; PS2:PS0 is ; 000 or 001 ; ; desired WDT rate ;Bank 0 CHANGING PRESCALER (WDT→ ...
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... TIMER1 MODULE WITH GATE CONTROL The rfPIC12F675 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • ...
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... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2003 Microchip Technology Inc. rfPIC12F675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...
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... REGISTER 5-1: T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 R/W-0 — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = Timer1 T1G pin is low 0 = Timer1 is on bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits ...
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... Bit 5 Bit 4 Bit 3 Bit 2 T0IE INTE GPIE T0IF — — CMIF — — — CMIE — Preliminary rfPIC12F675 time before use. Thus, Value on Value on Bit 1 Bit 0 all other POR, BOD RESETS INTF GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — ...
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... NOTES: DS70091A-page 32 Preliminary 2003 Microchip Technology Inc. ...
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... The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator. R-0 U-0 R/W-0 R/W-0 — CINV CIS W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary rfPIC12F675 R/W-0 R/W-0 R/W-0 CM2 CM1 CM0 bit Bit is unknown DS70091A-page 33 ...
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... Comparator Operation A single comparator is shown in Figure 6-1, along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input the output of the comparator is a digital low level. When the analog input at V ...
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... Multiplexed Input with Internal Reference and Output CM2:CM0 = 101 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D Multiplexed Input with Internal Reference CM2:CM0 = 110 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D Preliminary rfPIC12F675 Off (Read as '0') COUT From CV REF Module CIS = 0 CIS = 1 COUT REF From CV Module CIS = 0 CIS = 1 COUT REF From CV Module DS70091A-page 35 ...
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... Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 6-3. Since the analog pins are connected to a digital output, they have reverse biased diodes and V . The analog input, therefore, must be between and the input voltage deviates from this ...
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... Comparator Reset mode, CM2:CM0 = 000 and the voltage reference to its off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible. The Preliminary rfPIC12F675 REF DD = (VR3:VR0 / 24 REF ...
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... REGISTER 6-2: VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 VREN bit 7 REF bit 7 VREN REF circuit powered REF circuit powered down bit 6 Unimplemented: Read as '0' REF bit 5 VRR: CV Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as '0' ...
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... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representa- tion of that signal. The rfPIC12F675 has four analog inputs, multiplexed into one sample and hold circuit. FIGURE 7-1: A/D BLOCK DIAGRAM REF V GP0/AN0 REF GP1/AN1/V ...
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... TABLE 7-1: T vs. DEVICE OPERATING FREQUENCIES AD AD A/D Clock Source (T ) Operation ADCS2:ADCS0 000 OSC 2 T 100 OSC 4 T 001 OSC 8 T 101 OSC 16 T 010 OSC 32 T 110 OSC 64 T x11 A/D RC Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical T 2: These values violate the minimum required T 3: For faster conversion times, the selection of another clock source is recommended ...
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... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion STATUS bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. rfPIC12F675 U-0 U-0 R/W-0 R/W-0 — — CHS1 CHS0 W = Writable bit U = Unimplemented bit, read as ‘ ...
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... REGISTER 7-2: ANSEL — ANALOG SELECT REGISTER (ADDRESS: 9Fh) U-0 R/W-0 — ADCS2 bit 7 bit 7 Unimplemented: Read as ‘0’. bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = F OSC /2 001 = F OSC /8 010 = F OSC /32 x11 = F RC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = F ...
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... DD V Sampling Switch 0.6V ≤ LEAKAGE 0.6V ± 500 Preliminary rfPIC12F675 the minimum acquisition time, ACQ , see Mid-Range Reference Manual SS C HOLD = DAC capacitance = 120 Sampling Switch (kΩ) DS70091A-page 43 ...
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... A/D Operation During SLEEP The A/D converter module can operate during SLEEP. This requires the A/D clock source to be set to the internal RC oscillator. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion ...
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... EEDATA • EEADR EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. The rfPIC12F675 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. REGISTER 8-1: EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
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... EEADR The EEADR register can address maximum of 128 bytes of data EEPROM. Only seven of the eight bits in the register (EEADR<6:0>) are required. The MSb (bit 7) is ignored. The upper bit should always be ‘0’ to remain upward compatible with devices that have more data EEPROM memory ...
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... Power-up Timer EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: • brown-out • power glitch • software malfunction Preliminary rfPIC12F675 WRITE VERIFY STATUS,RP0 ;Bank 0 ;Any code STATUS,RP0 ;Bank 1 READ EEDATA,W ;EEDATA not changed ...
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... DATA EEPROM OPERATION DURING CODE PROTECT Data memory can be code protected by programming the CPD bit to ‘0’. When the data memory is code protected, the CPU is able to read and write data to the Data EEPROM recommended to code protect the program memory when code protecting data memory ...
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... The rfPIC12F675 is capable of transmitting data by Amplitude Shift Keying (ASK) or Frequency Shift Keying (FSK). The rfPIC12F675 is a radio frequency (RF) emitting device. Wireless RF devices are governed by a country’s regulating agency. For example, in the United States it is the Federal Communications Committee ...
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... A = 25°C, RFEN = 1, V Preliminary ASK pin enables the PA, FSK OUT and FSK pins are not ASK CRYSTAL CIRCUIT XTAL X1 rfPIC12F675K/F/H C1 (1) Transmit Frequency (MHz) XTAL ( 433.646 433.618 433.595 433.5895 433.5856 433.579 DDRF = 3V, 2003 Microchip Technology Inc. ...
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... A EN DDRF = 25° 3V, f Preliminary rfPIC12F675 ASK pin should be tied high to FSK CRYSTAL CIRCUIT XTAL X1 C2 FSKOUT C1 rfPIC12F675K/F/H FREQUENCY PULLING C1 C1||C2 FSK FSK = 1 DATA = 0 Load Capacitance (pF) ( Freq (MHz) / Dev (kHz) 433.625 / 21 433.614 / 14 433.608 / 10 433.604 / 8 433.600 / 5.5 — XTAL = 13 ...
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... SSRF L1 +V 120 4.7 kΩ 100 BT1 + CR2032 - 3V Lithium Cell DD GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/V /ICSPCLK REF GP2/AN2/T0CKI/INT/COUT PP DATA DATA U1 DDRF rfPIC12F675K SSRF C2 1000 120 4.7 kΩ 100 BT1 + CR2032 - 3V Lithium Cell Preliminary ...
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... The REFCLK output can connect directly to the T0CKI or T1CKI. The REFCLK output frequency is the crystal oscillator divided the rfPIC12F675K and rfPIC12F675F. For the rfPIC12F675H the crystal oscillator is divided by 8. Layout considerations - Keep the clock trace short and narrow yet as far as possible from other traces to reduce capacitance and the associated current draw ...
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... The RFEN pin has an internal pull-down resistor. 9.10 Low Voltage Output Disable The rfPIC12F675 transmitter has a built in low voltage disable centered at about 1.85V. If the supply voltage drops below this voltage the power amplifier is disabled to prevent uncontrolled transmissions. ...
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... SPECIAL FEATURES OF THE CPU Certain special circuits that deal with the needs of real time applications are what sets a microcontroller apart from other processors. The rfPIC12F675 Family has a host of such features intended to: • maximize system reliability • minimize cost through elimination of external components • ...
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... LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as specified in the rfPIC12F675 Programming Specification. These bits are reflected in an export of the configuration word. Microchip Development Tools maintain all calibration bits to factory settings ...
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... Oscillator Configurations 10.2.1 OSCILLATOR TYPES The rfPIC12F675 can be operated in eight different Oscillator Option modes. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC External Resistor/Capacitor (2 modes) • ...
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... Tools maintain all calibration bits to factory ) values settings. EXAMPLE 10-1: bsf call movwf bcf 10.2.6 CLKOUT The rfPIC12F675 devices can be configured to provide a clock out signal in the INTOSC and RC oscillator modes. When configured, the oscillator frequency divided by four (F CLKOUT pin synchronize other logic. Internal Clock Preliminary OSCILLATOR Z Section 13 ...
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... RESET The rfPIC12F675 differentiates between various kinds of RESET: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during SLEEP d) MCLR Reset during normal operation e) MCLR Reset during SLEEP f) Brown-out Detect (BOD) Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “ ...
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... MCLR The rfPIC12F675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. ...
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... Then bringing MCLR high will begin execution immediately (see Figure 10-8). This is useful for testing purposes or to synchronize more than one rfPIC12F675 device operating in parallel. Table 10-6 shows the RESET conditions for some special registers, while Table 10-7 shows the RESET conditions for all the registers. ...
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... TABLE 10-3: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration PWRTE = 0 PWRT XT, HS 1024•T RC, EC, INTOSC T PWRT TABLE 10-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOD Legend unchanged unknown TABLE 10-5: ...
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... Preliminary rfPIC12F675 • Wake-up from SLEEP through interrupt • Wake-up from SLEEP through WDT time-out uuuu uuuu — uuuu uuuu ( (4) uuuq quuu uuuu uuuu ...
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... FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ...
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... Interrupts The rfPIC12F675 has 7 sources of interrupt: • External Interrupt GP2/INT • TMR0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt • TMR1 Overflow Interrupt • EEPROM Data Write Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits ...
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... FIGURE 10-10: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF ADIE EEIF EEIE DS70091A-page 66 T0IF Wake-up (If in SLEEP mode) T0IE INTF INTE GPIF GPIE PEIE GIE Preliminary 2003 Microchip Technology Inc. ...
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... See Section 7.0 for operation of the A/D converter interrupt. T0IE Interrupt Latency 2 PC+1 PC+1 Inst (PC+1) — Inst (PC) Dummy Cycle CY . Synchronous latency = where T Preliminary rfPIC12F675 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle CY = instruction cycle time. Latency DS70091A-page 67 ...
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... TABLE 10-8: SUMMARY OF INTERRUPT REGISTERS Address Name Bit 7 Bit 6 0Bh, 8Bh INTCON GIE PEIE 0Ch PIR1 EEIF ADIF 8Ch PIE1 EEIE ADIE Legend unknown unchanged unimplemented read as '0 value depends upon condition. Shaded cells are not used by the Interrupt module. 10.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack ...
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... Note: The entire data EEPROM and FLASH program memory will be erased when the code protection is turned off. The INTOSC calibration data is also erased. See rfPIC12F675 Programming Specification for more information. Preliminary rfPIC12F675 Data Bus 8 SYNC 2 ...
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... Power-Down Mode (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running • PD bit in the STATUS register is cleared • TO bit is set • Oscillator driver is turned off • I/O ports maintain the status they had before ...
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... The socket can even be left in the final layout for in-circuit production programming. A simple method for programming is to solder all the rfPIC12F675 pins to the board and move the 8-pin DIP socket to the back side of the board. Then use the 8-pin standoff from the MPLAB ICE 2000 emulator to connect the PCB to a programmer such as the Pro ® ...
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... IN-CIRCUIT DEBUGGING USING THE PARALLEL DIP SOCKET DVA12XP081 or AC162050 Standoff rfPIC12F675 FIGURE 10-17: IN-CIRCUIT PROGRAMMING USING THE PARALLEL DIP SOCKET rfPIC12F675 DS70091A-page 72 TABLE 10-10: DEBUGGER RESOURCES I/O pins Stack Program Memory For more information, see 8-Pin MPLAB ICD 2 Header Information Sheet (DS51292) available on Microchip’s website (www ...
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... Byte-oriented operations • Bit-oriented operations • Literal and control operations Each rfPIC12F675 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 11-1, while the various opcode fields are summarized in Table 11-1 ...
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... TABLE 11-2: rfPIC12F675 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2003 Microchip Technology Inc. rfPIC12F675 BCF Bit Clear f Syntax: [label] BCF 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ → (f<b>) ...
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... CALL Call Subroutine Syntax: [ label ] CALL k 0 ≤ k ≤ 2047 Operands: Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immedi- ate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH ...
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... Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'. 2003 Microchip Technology Inc. rfPIC12F675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (destination), ...
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... MOVF Move f Syntax: [ label ] MOVF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (f) → (destination) Operation: Status Affected: Z Description: The contents of register f are moved to a destination dependant upon the status destination is W register the destination is file register f itself useful to test a file register, since status flag Z is affected ...
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... Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f 2003 Microchip Technology Inc. rfPIC12F675 SLEEP Syntax: [ label ] SLEEP Operands: None 00h → WDT, Operation: 0 → ...
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... SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (f<3:0>) → (destination<7:4>), Operation: (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register 'f' are exchanged the result is placed in the W register the result is placed in register 'f' ...
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... PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2003 Microchip Technology Inc. rfPIC12F675 12.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows based application that contains: • ...
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... MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 85
... Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. rfPIC12F675 12.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...
Page 86
... PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program- mer PICSTART Plus development programmer ...
Page 87
... PICDEM MSC demo boards for Switching mode power supply, high power IR driver, delta sigma ADC, and flow rate sensor Check the Microchip web page and the latest Product Line Card for the complete list of demonstration and ® IDE (Inte- evaluation kits. ® Preliminary rfPIC12F675 TM development DS70091A-page 85 ...
Page 88
... NOTES: DS70091A-page 86 Preliminary 2003 Microchip Technology Inc. ...
Page 89
... Microchip Technology Inc. ............................................................................................... -0.3 to +7.0V SS ............................................................................ -0. SSRF .............................................-0. )...............................................................................................................± ).........................................................................................................± ∑( OLRF ) should be used when applying a "low" level to the MCLR pin, rather than pulling Preliminary rfPIC12F675 DD + 0.3V) DDRF + 0.3V) - ∑ ∑ {(V DDRF DDRF OHRF DDRF DS70091A-page 87 ...
Page 90
... A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 13-2: rfPIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. ...
Page 91
... FIGURE 13-3: rfPIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2003 Microchip Technology Inc Microcontroller Frequency (MHz) Preliminary rfPIC12F675 20 DS70091A-page 89 ...
Page 92
... Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40°C ≤ T Min Typ† Max Units F 2.0 — 5.5 V rfPIC12F675 with A/D off 2.2 — 5.5 V rfPIC12F675 with A/D on, 0°C to +125°C 2.5 — 5.5 V rfPIC12F675 with A/D on, -40°C to +125°C 3.0 — 5 4.5 — 5 1.5* — ...
Page 93
... DC Characteristics: rfPIC12F675-I (Industrial) Param Device Characteristics No. (3) DD D010 Supply Current (I ) D011 D012 D013 D014 D015 D016 D017 † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all I from rail to rail ...
Page 94
... DC Characteristics: rfPIC12F675-I (Industrial) Param Device Characteristics No. D020 Power-down Current ( D021 D022 D023 D024 D025 D026 D027 Power-down RF Current (3) PDRF (I ) † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 95
... DD measurements in Active Operation mode are: OSC1 = external square wave MCLR = DDRF from V and I from V Preliminary rfPIC12F675 ≤ +125°C for extended Conditions Note OSC kHz LP Oscillator Mode F OSC = 1 MHz XT Oscillator Mode OSC MHz XT Oscillator Mode OSC ...
Page 96
... PIC12F675 DC Characteristics: rf Param Device Characteristics No. D020E Power-down Current ( D021E D022E D023E D024E D025E D026E D027E Power-down RF Current (3) PDRF (I ) † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 97
... DD DD DDRF from V and I from V Preliminary rfPIC12F675 Conditions Note ASK Power Step 0, RFEN=DATA =1 ASK Power Step 1, RFEN=DATA =1 Power Step 2, RFEN=DATA ASK =1 ASK Power Step 3, RFEN=DATA =1 ASK Power Step 4, RFEN=DATA =1 DDRF . Conditions Note Power Step 0, RFEN=DATA ASK =1 Power Step 1, RFEN=DATA ...
Page 98
... DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage IL V I/O ports D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) D033A OSC1 (HS mode) ASK FSK D034 DATA , DATA ...
Page 99
... DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended) (Cont.) DC CHARACTERISTICS Param Sym Characteristic No. Capacitive Loading Specs on Output Pins D100 C OSC2 pin OSC2 IO D101 C All I/O pins Data EEPROM Memory D D120 E Byte Endurance D120A E D Byte Endurance DRW DD D121 V V for Read/Write DEW D122 T Erase/Write cycle time ...
Page 100
... TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
Page 101
... AC CHARACTERISTICS: rfPIC12F675 (INDUSTRIAL, EXTENDED) FIGURE 13-5: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. OSC F External CLKIN Frequency Oscillator Frequency OSC 1 T External CLKIN Period (1) Oscillator Period Instruction Cycle Time 3 TosL, External CLKIN (OSC1) High TosH ...
Page 102
... TABLE 13-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Param Sym Characteristic No. F F10 OSC Internal Calibrated INTOSC Frequency F14 T IOSC Oscillator Wake-up from ST SLEEP start-up time* * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 103
... OSC T + 200 — — — 50 — — 100 — 0 — — 10 — — — OSC Preliminary rfPIC12F675 New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ...
Page 104
... FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING DD V MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset I/O Pins FIGURE 13-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS DD V VDD B (Device in Brown-out Detect) RESET (due to BOD) Note delay only if PWRTE bit in configuration word is programmed to ‘0’. ...
Page 105
... These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2003 Microchip Technology Inc. rfPIC12F675 Min Typ† Max Units µs 2 — ...
Page 106
... FIGURE 13-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 13-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width 42* Tt0P T0CKI Period 45* Tt1H T1CKI High Time Synchronous, No Prescaler ...
Page 107
... V /24* — LSb DD DD — V /32 — LSb ± 1/2 — — LSb ± 1/2* — — LSb — 2k* — — — 10* Preliminary rfPIC12F675 Comments V Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0) Ω µs DS70091A-page 105 ...
Page 108
... TABLE 13-8: rfPIC12F675 A/D CONVERTER CHARACTERISTICS: Param Sym Characteristic No. R A01 N Resolution ABS A02 E Total Absolute Error* IL A03 E Integral Error DL A04 E Differential Error FS A05 E Full Scale Range A06 E OFF Offset Error GN A07 E Gain Error A10 — Monotonicity REF A20 V Reference Voltage A20A ...
Page 109
... FIGURE 13-10: rfPIC12F675 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO OSC 134 (T Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 13-9: rfPIC12F675 A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. AD 130 T A/D Clock Period ...
Page 110
... OSC ( A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 13-10: rfPIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param Sym Characteristic No. AD 130 T A/D Clock Period 130 T A/D Internal RC AD Oscillator Period ...
Page 111
... TABLE 13-11: rfPIC12F675K RF TRANSMITTER SPECIFICATIONS (315 MHz) RF Transmitter Specifications Sym Characteristics C F VCO Frequency XTAL F Crystal Frequency F REF Reference Frequency L C Load Capacitance O C Static Capacitance S R Series Resistance SPUR A Spurious response ∆F VDD Frequency Stability vs V DDRF ∆F TA Frequency Stability vs Temp ∆ ...
Page 112
... TABLE 13-12: rfPIC12F675F RF TRANSMITTER SPECIFICATIONS (434 MHz) RF Transmitter Specifications Sym Characteristics C F VCO Frequency XTAL F Crystal Frequency F REF Reference Frequency L C Load Capacitance O C Static Capacitance S R Series Resistance SPUR A Spurious response ∆F VDD Frequency Stability vs V DDRF ∆F TA Frequency Stability vs Temp ∆ ...
Page 113
... TABLE 13-13: rfPIC12F675H RF TRANSMITTER SPECIFICATIONS (868/915 MHz) RF Transmitter Specifications Sym Characteristics C F VCO Frequency XTAL F Crystal Frequency F REF Reference Frequency L C Load Capacitance O C Static Capacitance S R Series Resistance SPUR A Spurious response ∆F VDD Frequency Stability vs V DDRF ∆F TA Frequency Stability vs Temp ∆ ...
Page 114
... NOTES: DS70091A-page 112 Preliminary 2003 Microchip Technology Inc. ...
Page 115
... FIGURE 14-1: TYPICAL I PD 6.0E-09 5.0E-09 4.0E-09 3.0E-09 2.0E-09 1.0E-09 0.0E+00 2 2.5 FIGURE 14-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5 2003 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD Preliminary rfPIC12F675 DD - 5.5 85 5.0 5.5 DS70091A-page 113 ...
Page 116
... FIGURE 14-3: TYPICAL I PD 4.0E-06 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 FIGURE 14-4: MAXIMUM I PD 1.0E-07 9.0E-08 8.0E-08 7.0E-08 6.0E-08 5.0E-08 4.0E-08 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 DS70091A-page 114 vs. V OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD Preliminary 125 5.0 5.5 - 5.5 2003 Microchip Technology Inc. ...
Page 117
... FIGURE 14-5: MAXIMUM I PD 9.0E-07 8.0E-07 7.0E-07 6.0E-07 5.0E-07 4.0E-07 3.0E-07 2.0E-07 1.0E-07 0.0E+00 2.0 2.5 FIGURE 14-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 2003 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD Preliminary rfPIC12F675 85 5.0 5.5 125 5.0 5.5 DS70091A-page 115 ...
Page 118
... FIGURE 14-7: TYPICAL I PD 130 120 110 100 3.5 FIGURE 14-8: TYPICAL I PD 1.8E-05 1.6E-05 1.4E-05 1.2E-05 1.0E-05 8.0E-06 6.0E-06 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 DS70091A-page 116 WITH BOD ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical BOD 4.5 V (V) DD WITH CMP ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical Comparator ...
Page 119
... FIGURE 14-9: TYPICAL I PD 5.0E-09 4.5E-09 4.0E-09 3.5E-09 3.0E-09 2.5E-09 2.0E-09 1.5E-09 1.0E-09 5.0E-10 0.0E+00 2 2.5 FIGURE 14-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 2003 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A 3.5 4 4.5 V (V) DD Preliminary rfPIC12F675 - 5 5.5 DS70091A-page 117 ...
Page 120
... FIGURE 14-11: TYPICAL I PD 3.5E-06 3.0E-06 2.5E-06 2.0E-06 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 FIGURE 14-12: TYPICAL KHZ, C1 AND C2=50 pF) 1.20E-05 1.00E-05 8.00E-06 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 DS70091A-page 118 WITH A/D ENABLED vs. V OVER TEMP (+125°C) DD Typical A 3.5 4 4.5 ( WITH T1 OSC ENABLED vs Typical 3.0 3.5 4.0 4.5 ( Preliminary 125 5 5.5 OVER TEMP (-40°C TO +125°C), ...
Page 121
... Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT 3.5 4 4.5 V (V) DD Preliminary rfPIC12F675 - 125 5 5.5 - 125 5 5.5 DS70091A-page 119 ...
Page 122
... FIGURE 14-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1µF AND 0.01µF DECOUPLING (V 4.20E+06 4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 -40°C FIGURE 14-16: MAXIMUM AND MINIMUM INTOSC FREQ vs. V DECOUPLING (+25°C) 4.20E+06 4.15E+06 4.10E+06 4.05E+06 4.00E+06 3.95E+06 3.90E+06 3.85E+06 3.80E+06 2 ...
Page 123
... FIGURE 14-17: TYPICAL WDT PERIOD vs 2.5 2003 Microchip Technology Inc. (-40°C TO +125°C) DD WDT Time-out 3 3.5 4 4.5 V (V) DD Preliminary rfPIC12F675 - 125 5 5.5 DS70091A-page 121 ...
Page 124
... NOTES: DS70091A-page 122 Preliminary 2003 Microchip Technology Inc. ...
Page 125
... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2003 Microchip Technology Inc. rfPIC12F675 Example rfPIC™ 12F675H 0314CBP ...
Page 126
... Package Type: 20-Lead SSOP 20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP β Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle ...
Page 127
... APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. 2003 Microchip Technology Inc. rfPIC12F675 Preliminary DS70091A-page 125 ...
Page 128
... NOTES: DS70091A-page 126 Preliminary 2003 Microchip Technology Inc. ...
Page 129
INDEX A A/D ...................................................................................... 39 Acquisition Requirements ........................................... 43 Block Diagram............................................................. 39 Calculating Acquisition Time....................................... 43 Configuration and Operation....................................... 39 Effects of a RESET ..................................................... 44 Internal Sampling Switch (Rss) Impedance ................ 43 Operation During SLEEP ............................................ 44 PIC12F675 Converter ...
Page 130
BSF ............................................................................. 75 BTFSC ........................................................................ 75 BTFSS ........................................................................ 75 CALL ........................................................................... 76 CLRF........................................................................... 76 CLRW ......................................................................... 76 CLRWDT..................................................................... 76 COMF ......................................................................... 76 DECF .......................................................................... 76 DECFSZ...................................................................... 77 GOTO ......................................................................... 77 INCF............................................................................ 77 INCFSZ ....................................................................... 77 IORLW ........................................................................ 77 IORWF ........................................................................ ...
Page 131
Timer1 Module with Gate Control ....................................... 28 Timing Diagrams CLKOUT and I/O....................................................... 101 External Clock............................................................. 99 INT Pin Interrupt.......................................................... 67 PIC12F675 A/D Conversion (Normal Mode)............. 107 PIC12F675 A/D Conversion Timing (SLEEP Mode) .......................................................... 108 RESET, Watchdog Timer, Oscillator Start-up Timer ...
Page 132
NOTES: DS70091A-page 130 Preliminary 2003 Microchip Technology Inc. ...
Page 133
... Microchip's development systems software products. Plus, this line provides information on how customers ® ® can receive the most current upgrade kits.The Hot Line or Microsoft Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Preliminary rfPIC12F675 092002 DS70091A-page 131 ...
Page 134
... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: rfPIC12F675 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
Page 135
... Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. XXX Examples: Pattern a) rfPIC12F675F – E/SS 301 = Extended Temp., SSOP package, 434 MHz, QTP pattern #301 b) rfPIC12F675HT – I/SS = Industrial Temp., SSOP package, 868 MHz, Tape and Reel Preliminary ...
Page 136
ORLDWIDE W AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Atlanta 3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307 Boston 2 Lan Drive, Suite ...