K4T1G164QE-HCF7 Samsung, K4T1G164QE-HCF7 Datasheet - Page 22
Manufacturer Part Number
Specifications of K4T1G164QE-HCF7
14.0 General notes, which may apply for all AC parameters
1. DDR2 SDRAM AC timing reference load
Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre
sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally
a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with V
signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
2. Slew Rate Measurement Levels
a) Output slew rate for falling and rising edges is measured between V
(e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by
design, but is not necessarily tested on each device.
b) Input slew rate for single ended signals is measured from V
edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to -
500 mV for falling edges).
is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure 2.
Figure 1 - AC Timing Reference Load
- 250 mV and V
(DC) to V
(AC),min for rising edges and from V
Figure 2 - Slew Rate Test Load
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. The output timing reference voltage level for differential
+ 250 mV for single ended signals. For differential signals
(DC) to V
Rev. 1.1 December 2008
(AC),max for falling