K4T1G164QE-HCF7

Manufacturer Part NumberK4T1G164QE-HCF7
ManufacturerSamsung
K4T1G164QE-HCF7 datasheet
 


Specifications of K4T1G164QE-HCF7

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K4T1G044QE
K4T1G084QE
K4T1G164QE
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to V
through a 20 Ω to 10 kΩ resistor to insure proper operation.
DQS
DQS
DQ
DM
CK
CK/CK
CK
DQS/DQS
DQ
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to V
.
SS
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
tDQSH
tDQSL
DQS
DQS
tWPRE
V
(AC)
IH
D
D
V
(AC)
IL
tDS
tDS
V
(AC)
IH
DMin
DMin
V
(AC)
IL
Figure 3 - Data Input (Write) Timing
tCH
tCL
DQS
DQS
tRPRE
Q
Q
tDQSQ(max)
tQH
Figure 4 - Data Output (Read) Timing
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DDR2 SDRAM
. In differential mode, these
REF
tWPST
V
(DC)
IH
D
D
V
(DC)
IL
tDH
tDH
V
(DC)
IH
DMin
DMin
V
(DC)
IL
tRPST
Q
Q
tDQSQ(max)
tQH
Rev. 1.1 December 2008
SS