K4T1G164QE-HCF7

Manufacturer Part NumberK4T1G164QE-HCF7
ManufacturerSamsung
K4T1G164QE-HCF7 datasheet
 

Specifications of K4T1G164QE-HCF7

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K4T1G044QE
K4T1G084QE
K4T1G164QE
Table 5 - Derating values for DDR2-667, DDR2-800
2.0 V/ns
∆tIS
4.0
+150
3.5
+143
3.0
+133
2.5
+120
2.0
+100
1.5
+67
1.0
0
0.9
-5
Command/
0.8
-13
Address Slew
0.7
-22
rate(V/ns)
0.6
-34
0.5
-60
0.4
-100
0.3
-168
0.25
-200
0.2
-325
0.15
-517
0.1
-1000
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS
and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
the actual signal is always earlier than the nominal slew rate line between shaded ’V
Figure 13). If the actual signal is later than the nominal slew rate line anywhere between shaded ’V
the actual signal from the ac level to dc level is used for derating value (see Figure 14).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
the actual signal is always later than the nominal slewrate line between shaded ’dc to V
ure 15). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V
the actual signal from the dc level to V
(DC) level is used for derating value (see Figure 16).
REF
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
transition) a valid input signal is still required to complete the transition and reach V
For slew rates in between the values listed in Tables 4 and 5, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
CK, CK Differential Slew Rate
1.5 V/ns
∆tIH
∆tIS
∆tIH
+94
+180
+124
+89
+173
+119
+83
+163
+113
+75
+150
+105
+45
+130
+75
+21
+97
+51
0
+30
+30
-14
+25
+16
-31
+17
-1
-54
+8
-24
-83
-4
-53
-125
-30
-95
-188
-70
-158
-292
-138
-262
-375
-170
-345
-500
-295
-470
-708
-487
-678
-1125
-970
-1095
(DC) to ac region’, use nominal slew rate for derating value (see
REF
(DC) region’, use nominal slew rate for derating value (see Fig-
REF
(AC).
IH/IL
35 of 45
DDR2 SDRAM
1.0 V/ns
Units
∆tIS
∆tIH
+210
+154
ps
+203
+149
ps
+193
+143
ps
+180
+135
ps
+160
+105
ps
+127
+81
ps
+60
+60
ps
+55
+46
ps
+47
+29
ps
+38
+6
ps
+26
-23
ps
0
-65
ps
-40
-128
ps
-108
-232
ps
-140
-315
ps
-265
-440
ps
-457
-648
ps
-940
-1065
ps
(DC) and the first crossing of V
REF
(DC) and the first crossing of V
REF
IL
(DC) to ac region’, the slew rate of a tangent line to
REF
(DC)max and the first crossing of V
IL
(DC)min and the first crossing of V
IH
(DC) region’, the slew rate of a tangent line to
REF
(AC) at the time of the rising clock
IH/IL
Rev. 1.1 December 2008
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(AC)min.
IH
(AC)max. If
(DC).
REF
(DC). If
REF