K4T1G164QE-HCF7 Samsung, K4T1G164QE-HCF7 Datasheet - Page 4
Manufacturer Part Number
Specifications of K4T1G164QE-HCF7
1.0 Ordering Information
1. Speed bin is in order of CL-tRCD-tRP.
2. RoHS Compliant.
3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
4. “C” of Part number(13th digit) stands normal, and “L” stands for Low power products.
2.0 Key Features
• JEDEC standard V
= 1.8V ± 0.1V Power Supply
= 1.8V ± 0.1V
• 333MHz f
for 667Mb/sec/pin, 400MHz f
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- 50ohm ODT
- High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
< 95 °C
3.9us at 85°C < T
• All of products are Lead-Free, Halogen-Free, and RoHS com-
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x
8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x8) device receive 14/
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V V
The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in
Note : The functionality described and the timing specifications included in
this data sheet are for the DLL Enabled mode of operation.
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Rev. 1.1 December 2008