AS7C31025B-12TJC Alliance Semiconductor, AS7C31025B-12TJC Datasheet

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AS7C31025B-12TJC

Manufacturer Part Number
AS7C31025B-12TJC
Description
Manufacturer
Alliance Semiconductor
Datasheets

Specifications of AS7C31025B-12TJC

Case
TSOP32
Date_code
06+
3/24/04, v. 1.3
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
• Low power consumption: ACTIVE
• Low power consumption: STANDBY
• 6 T 0.18 u CMOS technology
Selection guide
Logic block diagram
March 2004
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
- 252 mW / max @ 10 ns
- 18 mW / max CMOS
GND
V
A0
A1
A2
A3
A4
A5
A6
A7
A8
CC
Column decoder
512 x 256 x 8
Input buffer
(1,048,576)
Array
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Alliance Semiconductor
Control
circuit
-10
10
70
WE
OE
5
5
CE
I/O7
I/O0
Pin arrangement
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
-12
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
12
65
6
5
®
GND
I/O0
I/O1
V
I/O2
I/O3
WE
CE
A0
A1
A2
A3
A4
A5
A6
A7
CC
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
-15
15
60
7
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Copyright © Alliance Semiconductor. All rights reserved.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AS7C31025B
V
A16
A15
A14
A13
OE
I/O7
I/O6
GND
I/O5
I/O4
A12
A11
A10
A9
A8
-20
20
55
CC
8
5
P. 1 of 9
Unit
mA
mA
ns
ns

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