ADSP2189MKST-300 Analog Devices, ADSP2189MKST-300 Datasheet

ADSP2189MKST-300

Manufacturer Part Number

ADSP2189MKST-300

Description

Manufacturer

Analog Devices

Datasheet

1.ADSP2189MKST-300.pdf (32 pages)

Specifications of ADSP2189MKST-300

Case

QFP

Date_code

08+

Current page: 1 of 32
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ICE-Port is a trademark of Analog Devices, Inc.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

REV. A

FEATURES

PERFORMANCE

13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible (Easy to Use Alge-

192K Bytes of On-Chip RAM, Configured as 32K Words

Dual Purpose Program Memory for Both Instruction

Independent ALU, Multiplier/Accumulator and Barrel

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP

SYSTEM INTERFACE

Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;

16-Bit Internal DMA Port for High Speed Access to On-

4 MByte Memory Interface for Storage of Data Tables

8-Bit DMA to Byte Memory for Transparent Program

I/O Memory Interface with 2048 Locations Supports

Programmable Memory Strobe and Separate I/O

Programmable Wait-State Generation

Two Double-Buffered Serial Ports with Companding

Automatic Booting of On-Chip Program Memory from

75 MIPS Sustained Performance

Every Instruction Cycle

Power Dissipation with 200 CLKIN Cycle Recovery

from Power-Down Condition

braic Syntax), with Instruction Set Extensions

On-Chip Program Memory RAM and 48K Words On-

Chip Data Memory RAM

and Data Storage

Shifter Computational Units

Looping Conditional Instruction Execution

All Inputs Tolerate Up to 3.6 V, Regardless of Mode

Chip Memory (Mode Selectable)

and Program Overlays (Mode Selectable)

and Data Memory Transfers (Mode Selectable)

Parallel Peripherals (Mode Selectable)

Memory Space Permits “Glueless” System Design

Hardware and Automatic Data Buffering

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

GENERAL DESCRIPTION

The ADSP-2189M is a single-chip microcomputer optimized

for digital signal processing (DSP) and other high speed nu-

meric processing applications.

The ADSP-2189M combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities, and on-chip program and data

memory.

The ADSP-2189M integrates 192K bytes of on-chip memory

configured as 32K words (24-bit) of program RAM and 48K

words (16-bit) of data RAM. Power-down circuitry is also pro-

vided to meet the low power needs of battery operated portable

equipment. The ADSP-2189M is available in a 100-lead LQFP

package.

In addition, the ADSP-2189M supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (x squared),

biased rounding, result free ALU operations, I/O memory trans-

fers and global interrupt masking, for increased flexibility.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

DATA ADDRESS

GENERATORS

DAG 1

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

ALU

ARITHMETIC UNITS

Signaling

Final Systems

ADSP-2100 BASE

ARCHITECTURE

DAG 2

MAC

SHIFTER

SEQUENCER

FUNCTIONAL BLOCK DIAGRAM

PROGRAM

PROGRAM MEMORY DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

DATA MEMORY DATA

World Wide Web Site: http://www.analog.com

DSP Microcomputer

PROGRAM

MEMORY

SPORT 0

32K

24 BIT

SERIAL PORTS

POWER-DOWN

CONTROL

MEMORY

SPORT 1

MEMORY

DATA

48K

16 BIT

ADSP-2189M

PROGRAMMABLE

TIMER

FLAGS

AND

I/O

FULL MEMORY

CONTROLLER

EXTERNAL

INTERNAL

HOST MODE

ADDRESS

BYTE DMA

DATA

PORT

DATA

DMA

BUS

MODE

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