EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

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Classic EPLD Family Data Sheet
General
Description
Figure 8. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2 (3)
INPUT
1 (2)
CLK1
3
(4)
4
(5)
5
(6)
6
(7)
7
(8)
8
(9)
9
(10)
10
(12)
11
(13)
INPUT
756
EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins,
and 2 global clock pins (see
from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the
output of the macrocell or the I/O input. The CLK1 signal is a dedicated
global clock input for the registers in macrocells 9 through 16. The CLK2
signal is a dedicated global clock input for registers in macrocells 1
through 8.
Macrocell 9
Macrocell 10
Macrocell 11
Global
Bus
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Figure 9
shows the typical supply current (I
devices.
Figure 9. I
vs. Frequency of EP610 Devices
CC
100
10
Typical I
CC
Active (mA)
1.0
0.1
Figure
8). Each macrocell can access signals
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
) versus frequency of EP610
CC
Turbo
V
= 5.0 V
CC
T
= 25 C
A
Non-Turbo
1 kHz
10 kHz 100 kHz 1 MHz 10 MHz 80 MHz
Frequency
INPUT
(27)
23
CLK2
(16)
13
(26)
22
(25)
21
(24)
20
(23)
19
(22)
18
(21)
17
(20)
16
(18)
15
INPUT
(17)
14
Altera Corporation