EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

Date_code07+Packing_infoPLCC
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Features
Altera Corporation
High-performance, 24-macrocell Classic EPLD
Combinatorial speeds with t
Counter frequencies of up to 76.9 MHz
Pipelined data rates of up to 125 MHz
Programmable I/O architecture with up to 36 inputs or 24 outputs
EP910 and EP910I devices are pin-, function-, and programming file-
compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see
44-pin plastic J-lead chip carrier (PLCC)
40-pin ceramic and plastic dual in-line packages (CerDIP and
PDIP)
Figure 11. EP910 Package Pin-Out Diagrams
Package outlines are not drawn to scale. Windows in ceramic packages only.
6
5
4
3
2 1 44 43 42 41 40
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
NC
17
18 19 20 21 22 23 24 25 26 27 28
44-Pin PLCC
EP910
EP910I
EP910 EPLD
as fast as 12 ns
PD
Figure
11)
CLK1
1
INPUT
2
INPUT
3
INPUT
4
I/O
5
I/O
6
I/O
7
I/O
8
39
NC
I/O
9
38
I/O
I/O
10
37
I/O
I/O
11
36
I/O
I/O
12
35
I/O
I/O
13
34
I/O
I/O
14
33
I/O
I/O
15
32
I/O
I/O
16
31
I/O
INPUT
17
30
I/O
INPUT
18
29
I/O
INPUT
19
GND
20
40-Pin DIP
EP910
EP910I
VCC
40
INPUT
39
INPUT
38
INPUT
37
I/O
36
I/O
35
I/O
34
I/O
33
I/O
32
I/O
31
I/O
30
I/O
29
I/O
28
I/O
27
I/O
26
I/O
25
INPUT
24
INPUT
23
INPUT
22
CLK2
21
767