EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

Date_code07+Packing_infoPLCC
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Features
Figure 15. EP1810 Package Pin-Out Diagrams
Package outlines not drawn to scale. See
Windows in ceramic packages only.
L
K
J
H
G
Bottom
View
F
E
D
C
B
A
1
2
3
4
5
6
68-Pin PGA
EP1810
Altera Corporation
High-performance, 48-macrocell Classic EPLD
Combinatorial speeds with t
Counter frequencies of up to 50 MHz
Pipelined data rates of up to 62.5 MHz
Programmable I/O architecture with up to 64 inputs or 48 outputs
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see
68-pin ceramic pin-grid array (PGA)
68-pin plastic J-lead chip carrier (PLCC)
Table 32 on page 785
of this data sheet for PGA package pin-out information.
I/O
10
I/O
11
I/O
12
I/O
13
INPUT
14
INPUT
15
INPUT
16
CLK1/INPUT
17
VCC
18
CLK2/INPUT
19
INPUT
20
INPUT
21
INPUT
22
INPUT
23
INPUT
24
INPUT
25
I/O
26
7
8
9
10 11
EP1810 EPLD
as fast as 20 ns
PD
Figure
15)
I/O
60
I/O
59
I/O
58
57
I/O
INPUT
56
INPUT
55
54
INPUT
CLK4/INPUT
53
VCC
52
51
CLK3/INPUT
50
INPUT
INPUT
49
48
INPUT
47
I/O
46
I/O
45
I/O
44
I/O
68-Pin PLCC
EP1810
777