EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

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Notes to tables:
(1)
These values are specified in
(2)
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(3)
Measured with a device programmed as four 12-bit counters.
(4)
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
(5)
The f
values represent the highest frequency for pipelined data.
MAX
(6)
Sample-tested only for an output change of 500 mV.
Pin-Out
Information
Altera Corporation
Table 24 on page
781.
Table 32
provides pin-out information for EP1810 devices in 68-pin PGA
packages.
Table 32. EP1810 PGA Pin-Outs
Pin
Function
Pin
Function
A2
I/O
B9
A3
I/O
B10
A4
I/O
B11
A5
INPUT
C1
A6
C2
CLK4/INPUT
A7
CLK3/INPUT C10
A8
INPUT
C11
A9
I/O
D1
A10
I/O
D2
B1
I/O
D10
B2
I/O
D11
B3
I/O
E1
B4
INPUT
E2
B5
INPUT
E10
B6
E11
VCC
B7
INPUT
F1
B8
INPUT
F2
Classic EPLD Family Data Sheet
Pin
Function
Pin
I/O
F10
K4
GND
I/O
F11
I/O
K5
I/O
G1
I/O
K6
I/O
G2
I/O
K7
I/O
G10
I/O
K8
I/O
G11
I/O
K9
I/O
H1
I/O
K10 I/O
I/O
H2
I/O
K11 I/O
I/O
H10
I/O
L2
I/O
H11
I/O
L3
I/O
J1
I/O
L4
I/O
J2
I/O
L5
I/O
J10
I/O
L6
I/O
J11
I/O
L7
I/O
K1
I/O
L8
I/O
K2
I/O
L9
K3
I/O
L10 I/O
GND
Function
INPUT
INPUT
VCC
INPUT
INPUT
I/O
I/O
I/O
INPUT
CLK1/INPUT
CLK2/INPUT
INPUT
I/O
I/O
785