EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

Date_code07+Packing_infoPLCC
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Mode 0
In Mode 0, the register
is clocked by the global
clock signal. The
output is enabled by
the logic from the
product term.
Mode 1
In Mode 1, the output
is permanently enabled
and the register is
clocked by the product
term, which allows
gated clocks to be
generated.
Figure 3. Classic Feedback Multiplexer Configurations
Global Feedback Multiplexer
Q
Global
I/O
EP610
EP610I
EP910
EP910I
Altera Corporation
Figure 2. Classic Output Enable/Clock Select
AND
Array
OE = Product Term
CLK = Global
AND
Array
OE = Enabled
CLK = Product Term
Feedback Select
Each macrocell in a Classic device provides feedback selection that is
controlled by the feedback multiplexer. This feedback selection allows the
designer to feed either the macrocell output or the I/O pin input
associated with the macrocell back into the AND array. The macrocell
output can be either the Q output of the programmable register or the
combinatorial output of the macrocell. Different devices have different
feedback multiplexer configurations. See
Quadrant Feedback Multiplexer
Quadrant
EP1810
Classic EPLD Family Data Sheet
Output Enable/Clock
VCC
Select
Global
Clock
OE
CLK
Data
Q
CLR
Output Enable/Clock
Select
Global
VCC
Clock
OE
CLK
Data
Q
CLR
Figure
3.
Dual Feedback Multiplexer
Quadrant
Q
Global
I/O
EP1810
Macrocell
Output Buffer
Macrocell
Output Buffer
Q
I/O
749