EP910LI-35

Manufacturer Part NumberEP910LI-35
ManufacturerAltera Corporation
EP910LI-35 datasheet
 


Specifications of EP910LI-35

Date_code07+Packing_infoPLCC
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Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
t
and t
< 3 ns.
R
F
Inputs are driven at 3 V
for a logic high and
I/O Pin
0 V for a logic low.
All timing characteristics
Input Pin
are measured at 1.5 V.
Logic Array Input
Logic Array Output
Output Pin
Global Clock Pin
Global Clock at Register
Data from Logic Array
Clock Pin
Clock into Logic Array
Clock from Logic Array
Data from Logic Array
Register Output to Logic Array
Clock from Logic Array
Data from Logic Array
Output Pin
752
Input Mode
t
= t
PD1
IN
t
t
= t
IO
PD2
IO
t
IN
t
LAD
t
CLR
Global Clock Mode
t
t
CH
R
t
t
IN
ICS
t
t
H
SU
Array Clock Mode
t
t
R
ACH
t
IN
t
IC
t
t
ASU
AH
Output Mode
t
OD
+ t
+ t
LAD
OD
+ t
+ t
+ t
IN
LAD
OD
t
OD
t
t
CL
F
t
t
ACL
F
t
FD
t
t
ZX
XZ
High-Impedance
Tri-State
Altera Corporation