24LC512 Microchip Technology Inc., 24LC512 Datasheet

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24LC512

Manufacturer Part Number
24LC512
Description
SOP8
Manufacturer
Microchip Technology Inc.
Datasheets

Specifications of 24LC512

Date_code
09+

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Device Selection Table
Features:
• Single Supply with Operation Down to 1.7V for
• Low-Power CMOS Technology:
• 2-Wire Serial Interface, I
• Cascadable for up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 years
• Packages Include 8-lead PDIP, SOIJ and DFN
• Pb-Free and RoHS Compliant
• Temperature Ranges:
* 24XX512 is used in this document as a generic part
number for the 24AA512/24LC512/24FC512 devices.
© 2007 Microchip Technology Inc.
Note 1:
24AA512
24LC512
24FC512
24AA512 and 24FC512 Devices, 2.5V for
24LC512 Devices
- Active current 400 uA, typical
- Standby current 100 nA, typical
- Industrial (I):
- Automotive (E):-40°C to +125°C
Number
Part
2:
100 kHz for V
400 kHz for V
1.7-5.5V
1.7-5.5V
2.5-5.5V
Range
V
CC
-40°C to +85°C
(2)
512K I
CC
CC
2
C
Max. Clock
Frequency
< 2.5V
< 2.5V
400 kHz
400 kHz
1 MHz
Compatible
2
(1)
24AA512/24LC512/24FC512
C
Ranges
Temp.
I, E
CMOS Serial EEPROM
I
I
Description:
The Microchip Technology Inc. 24AA512/24LC512/
24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications and data acquisi-
tion. This device also has a page write capability of up
to 128 bytes of data. This device is capable of both
random and sequential reads up to the 512K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 4 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIJ and DFN packages.
Block Diagram
Package Type
V
SDA
I/O
A0
A1
A2
SS
Control
Logic
V
V
I/O
CC
SS
1
2
3
4
SCL
PDIP
A0 A1 A2
V
Memory
Control
A0
A1
A2
Logic
SS
8
7
6
5
WP
1
2
3
4
V
WP
SCL
SDA
CC
DFN
V
XDEC
A0
A1
A2
SS
8
7
6
5
V
WP
SCL
SDA
1
2
3
4
CC
DS21754H-page 1
SOIJ
HV Generator
Page Latches
Sense Amp.
R/W Control
EEPROM
Array
YDEC
8
7
6
5
V
WP
SCL
SDA
CC

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