A6801SAT

Manufacturer Part NumberA6801SAT
DescriptionDIP22
ManufacturerAllegro Micro Systems, Inc.
A6801SAT datasheet
 

Specifications of A6801SAT

Date_code05+  
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Timing Requirements and Specifi cations
(Logic Levels are V
CLEAR
STROBE
A
C
B
C
H
IN N
E
D
OUT N
50%
OUTPUT ENABLE
OUT
N
Key
A
Minimum data active time before Strobe enabled (Data Set-Up Time)
B
Minimum data active time after Strobe disabled (Data Hold Time)
C
Minimum Strobe pulse width
D
Maximum time between Strobe activation and transition from output on to output off*
E
Maximum time between Strobe activation and transition from output off to output on*
F
Maximum time between Clear activation and transition from output on to output off*
G
Minimum Clear pulse width
H
Minimum data pulse width
t
Output Enable to output off delay*
dis(BQ)
t
Output Enable to output on delay*
en(BQ)
*Conditions for output transition testing are: V
NOTE: Information present at an input is transferred
to its latch when the STROBE is high. A high CLEAR
input will set all latches to the output off condition
regardless of the data or STROBE input levels. A high
DABiC-5 Latched Sink Drivers
and Ground)
DD
G
B
F
HIGH = ALL OUTPUTS DISABLED (OFF)
t
en(BQ)
t
t
r
f
t
90%
dis(BQ)
50%
DATA
10%
Description
= 50 V, V
= 5 V, R1 = 500 Ω, C1 ≤ 30 pF.
CC
DD
OUTPUT ENABLE will set all outputs to the off con-
tdition, regardless of any other input conditions. When
the OUTPUT ENABLE is low, the outputs depend on
the state of their respective latches.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6800/A6801
C
A
B
H
E
Time (ns)
25
25
50
500
500
500
50
100
500
500
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