AD9433BSVZ125 Analog Devices, AD9433BSVZ125 Datasheet

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AD9433BSVZ125

Manufacturer Part Number
AD9433BSVZ125
Description
TQFP52
Manufacturer
Analog Devices
Datasheet

Specifications of AD9433BSVZ125

Date_code
05+
FEATURES
IF sampling up to 350 MHz
SNR: 67.5 dB, f
SFDR: 83 dBc, f
SFDR: 72 dBc, f
2 V p-p analog input range
On-chip clock duty cycle stabilization
On-chip reference and track-and-hold
SFDR optimization circuit
Excellent linearity
750 MHz full power analog bandwidth
Power dissipation: 1.35 W (typical) at 125 MSPS
Twos complement or offset binary data format
5.0 V analog supply operation
2.5 V to 3.3 V TTL/CMOS outputs
APPLICATIONS
Cellular infrastructure communication systems
Wideband carrier frequency systems
Communications test equipment
Radar and satellite ground systems
GENERAL INTRODUCTION
The AD9433 is a 12-bit, monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
designed for ease of use. The product operates up to a 125 MSPS
conversion rate and is optimized for outstanding dynamic per-
formance in wideband and high IF carrier systems.
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external refer-
ence or driver components are required for many applications.
The digital outputs are TTL-/CMOS-compatible, and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DNL: ±0.25 LSB (typical)
INL: ±0.5 LSB (typical)
3G single- and multicarrier receivers
IF sampling schemes
Point-to-point radios
LMDS, wireless broadband
MMDS base station units
Cable reverse path
IN
IN
IN
up to Nyquist at 105 MSPS
= 70 MHz at 105 MSPS
= 150 MHz at 105 MSPS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
A user-selectable, on-chip proprietary circuit optimizes
spurious-free dynamic range (SFDR) vs. signal-to-noise and
distortion (SINAD) ratio performance for different input signal
frequencies, providing as much as 83 dBc SFDR performance
over the dc to 70 MHz band.
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is user-
selectable for offset binary or twos complement and provides
an overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a 52-lead thin quad flat package (TQFP_EP) that
is specified over the industrial temperature range of −40°C to
+85°C. The AD9433 is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
ENCODE
ENCODE
12-Bit, 105 MSPS/125 MSPS,
V
AIN
AIN
IF Sampling.
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G wideband
cellular IF sampling receivers.
Pin-Compatibility with the AD9432.
The AD9433 has the same footprint and pin layout as the
AD9432 12-bit 80 MSPS/105 MSPS ADC.
SFDR Performance.
A user-selectable, on-chip circuit optimizes SFDR
performance as much as 83 dBc from dc to 70 MHz.
Sampling Rate.
At 125 MSPS, the AD9433 is ideally suited for wireless and
wired broadband applications such as LMDS/MMDS and
cable reverse path.
CC
FUNCTIONAL BLOCK DIAGRAM
ENCODE
TIMING
T/H
GND
©2001–2009 Analog Devices, Inc. All rights reserved.
VREFOUT
PIPELINE
Figure 1.
ADC
IF Sampling ADC
REF
VREFIN
12
STAGING
OUTPUT
AD9433
AD9433
www.analog.com
12
V
D11 TO D0
DFS
SFDR
MODE
DD

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