ADSP2115BSZ80

Manufacturer Part NumberADSP2115BSZ80
DescriptionQFP80
ManufacturerAnalog Devices
ADSP2115BSZ80 datasheet
 

Specifications of ADSP2115BSZ80

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ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
1
t
BR Hold after CLKOUT High
BH
1
t
BR Setup before CLKOUT Low
BS
Switching Characteristic:
t
CLKOUT High to DMS,
SD
PMS, BMS, RD, WR Disable
t
DMS, PMS, BMS, RD, WR
SDB
Disable to BG Low
t
BG High to DMS, PMS,
SE
BMS, RD, WR Enable
t
DMS, PMS, BMS, RD, WR
SEC
Enable to CLKOUT High
NOTES
1
If BR meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
BS
BH
a pulse width greater than 10 ns.
2
For 25 MHz only the minimum frequency dependency formula for t
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
CLKOUT
BR
CLKOUT
PMS, DMS
BMS, RD
WR
BG
13 MHz
13.824 MHz 16.67 MHz 20 MHz
Min Max Min Max
Min Max Min Max Min Max Min
24.2
23.1
20
17.5
39.2
38.1
35
32.5
39.2
38.1
35
0
0
0
0
0
0
0
0
9.2
8.1
5
2.5
= (0.25t
– 8.5).
SEC
CK
t
BH
t
BS
t
SD
t
SDB
Figure 31. Bus Request/Grant
–32–
Frequency
25 MHz
Dependency
Max
15
0.25t
+ 5
CK
30
0.25t
+ 20
CK
32.5
30
0.25t
CK
0
0
0
0
2
2
1.5
0.25t
– 10
CK
t
SEC
t
SE
Unit
ns
ns
+ 20 ns
ns
ns
ns
REV. B