ADSP2115BSZ80

Manufacturer Part NumberADSP2115BSZ80
DescriptionQFP80
ManufacturerAnalog Devices
ADSP2115BSZ80 datasheet
 


Specifications of ADSP2115BSZ80

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Page 34/64

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ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMORY WRITE
Parameter
Switching Characteristic:
t
Data Setup before WR High
DW
t
Data Hold after WR High
DH
t
WR Pulse Width
WP
t
WR Low to Data Enabled
WDE
t
A0–A13, DMS, PMS Setup before
ASW
WR Low
t
Data Disable before WR or RD Low
DDR
t
CLKOUT High to WR Low
CWR
t
A0–A13, DMS, PMS, Setup before WR
AW
Deasserted
t
A0–A13, DMS, PMS Hold after WR
WRA
Deasserted
t
WR High to RD or WR Low
WWR
Parameter
Switching Characteristic:
t
Data Setup before WR High
DW
t
Data Hold after WR High
DH
t
WR Pulse Width
WP
t
WR Low to Data Enabled
WDE
t
A0–A13, DMS, PMS Setup before WR Low
ASW
t
Data Disable before WR or RD Low
DDR
t
CLKOUT High to WR Low
CWR
t
A0–A13, DMS, PMS, Setup before WR
AW
Deasserted
t
A0–A13, DMS, PMS Hold after WR
WRA
Deasserted
t
WR High to RD or WR Low
WWR
NOTES
1
For 25 MHz only the minimum frequency dependency formula for t
w = wait states
t
.
CK
CLKOUT
A0 – A13
DMS, PMS
WR
D
RD
13 MHz
13.824 MHz 16.67 MHz
Min Max Min Max
Min
Max
25.5
23.2
17
9.2
8.1
5
30.5
28.2
22
0
0
0
9.2
8.1
5
9.2
8.1
5
14.2 29.2 13.1 28.1
10
25
35.7
32.2
23
10.2
9.1
6
33.5
31.2
25
Frequency Dependency
(CLKIN 25 MHz)
Min
0.5t
– 13 + w
CK
0.25t
– 10
CK
0.5t
– 8 + w
CK
0
1
0.25t
– 10
CK
1
0.25t
– 10
CK
0.25t
– 5
CK
0.75t
– 22 + w
CK
0.25t
– 9
CK
0.5t
– 5
CK
and t
= (0.25t
– 8.5).
ASW
DDR
CK
t
WRA
t
t
ASW
WP
t
AW
t
DH
t
CWR
t
DW
t
WDE
Figure 33. Memory Write
–34–
20 MHz
25 MHz
Min Max
Min Max Unit
12
7
ns
2.5
0
ns
17
12
ns
0
0
ns
1
2.5
1.5
ns
1
2.5
1.5
ns
7.5
22.5
5
20
ns
15.5
8
ns
3.5
1
ns
20
15
ns
Max
Unit
ns
ns
ns
ns
ns
0.25t
+ 10
ns
CK
ns
ns
ns
t
WWR
t
DDR
REV. B