ADSP2115BSZ80

Manufacturer Part NumberADSP2115BSZ80
DescriptionQFP80
ManufacturerAnalog Devices
ADSP2115BSZ80 datasheet
 


Specifications of ADSP2115BSZ80

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TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
t
BR Hold after CLKOUT High
BH
t
BR Setup before CLKOUT Low
BS
Switching Characteristic:
t
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
SD
t
DMS, PMS, BMS, RD, WR Disable to BG Low
SDB
t
BG High to DMS, PMS, BMS, RD, WR Enable
SE
t
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
SEC
NOTES
1
If BR meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
BS
BH
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
CLKOUT
BR
CLKOUT
PMS, DMS
BMS, RD
WR
BG
REV. B
10.24 MHz
Min
Max
1
29.4
1
44.4
44.4
0
0
14.4
t
BH
t
BS
t
SD
t
SDB
Figure 41. Bus Request/Grant
–47–
ADSP-21xx
Frequency
Dependency
Min
Max
0.25t
+ 5
CK
0.25t
+ 20
CK
0.25t
+ 20
CK
0.25t
– 10
CK
t
SEC
t
SE
Unit
ns
ns
ns
ns
ns
ns