ADSP2115BSZ80

Manufacturer Part NumberADSP2115BSZ80
DescriptionQFP80
ManufacturerAnalog Devices
ADSP2115BSZ80 datasheet
 

Specifications of ADSP2115BSZ80

Date_code08+  
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DATA
DATA
ADDRESS
ADDRESS
GENERATOR
GENERATOR
#1
#2
PMA BUS
14
DMA BUS
14
PMD BUS
24
DMD BUS
16
INPUT REGS
INPUT REGS
ALU
MAC
OUTPUT REGS
OUTPUT REGS
One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-21xx processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. There is also a master RESET signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. The ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
REV. B
INSTRUCTION
PROGRAM
DATA
REGISTER
MEMORY
MEMORY
SRAM
SRAM
or ROM
PROGRAM
SEQUENCER
24
16
BUS
EXCHANGE
COMPANDING
INPUT REGS
CIRCUITRY
SHIFTER
TRANSMIT REG
RECEIVE REG
OUTPUT REGS
SERIAL
16
PORT 0
(Not on ADSP-2105)
R Bus
5
Figure 1. ADSP-21xx Block Diagram
Serial Ports
The ADSP-21xx processors include two synchronous serial
ports (“SPORTs”) for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT0, SPORT1) except for the ADSP-2105,
which has only SPORT1.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
SCLK
RFS
TFS
DR
DT
The ADSP-21xx serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
–5–
ADSP-21xx
FLAGS
(ADSP-2111 Only)
3
BOOT
ADDRESS
TIMER
GENERATOR
PMA BUS
14
MUX
DMA BUS
PMD BUS
24
MUX
DMD BUS
HOST
PORT
CONTROL
TRANSMIT REG
RECEIVE REG
HOST
SERIAL
PORT
PORT 1
DATA
HOST INTERFACE PORT
5
(ADSP-2111 Only)
Function
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
11
EXTERNAL
HOST PORT
BUS
16