ADSP2115KP80

Manufacturer Part NumberADSP2115KP80
DescriptionPLCC-68
ManufacturerAnalog Devices
ADSP2115KP80 datasheet
 


Specifications of ADSP2115KP80

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TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
Memory
Device
Specification
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
REV. B
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
ADSP-21xx
Timing
Timing
Parameter
Parameter
Definition
t
A0–A13, DMS, PMS Setup before WR Low
ASW
t
A0–A13, DMS, PMS Setup before WR Deasserted
AW
t
A0–A13, DMS, PMS Hold after WR Deasserted
WRA
t
Data Setup before WR High
DW
t
Data Hold after WR High
DH
t
RD Low to Data Valid
RDD
t
A0–A13, DMS, PMS, BMS to Data Valid
AA
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ADSP-21xx