ADSP2115KP80 Analog Devices, ADSP2115KP80 Datasheet - Page 40

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ADSP2115KP80

Manufacturer Part Number
ADSP2115KP80
Description
PLCC-68
Manufacturer
Analog Devices
Datasheet

Specifications of ADSP2115KP80

Date_code
01+
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
HOST INTERFACE PORT
Multiplexed Data & Address (HMD1 = 1)
Read Strobe & Write Strobe (HMD0 = 0)
Parameter
Timing Requirement:
t
ALE Pulse Width
HALP
t
HAD15-0 Address Setup before ALE Low
HASU
t
HAD15-0 Address Hold after ALE Low
HAH
t
Start of Write or Read after ALE Low
HALS
t
HAD15-0 Data Setup before End of Write
HDSU
t
HAD15-0 Data Hold after End of Write
HWDH
5
t
Read or Write Pulse Width
HRWP
Switching Characteristic:
t
HACK Low after Start of Write or Read
HSHK
t
HACK Hold after End of Write or Read
HKH
t
HAD15-0 Data Enabled after Start of Read
HDE
t
HAD15-0 Data Valid after Start of Read
HDD
t
HAD15-0 Data Hold after End of Read
HRDH
t
HAD15-0 Data Disabled after End of Read
HRDD
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
13.0 MHz
16.67 MHz
Min Max
Min Max
15
15
5
5
2
2
1, 2
15
15
3
8
8
3
3
3
30
30
1, 2
0
20
0
3, 4
0
20
0
2
0
0
2
23
4
0
0
4
10
–40–
20 MHz
No Frequency
Min Max
Dependency
15
5
2
15
8
3
30
20
0
20
20
0
20
0
23
23
0
10
10
REV. B
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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