ADSP2115KP80

Manufacturer Part NumberADSP2115KP80
DescriptionPLCC-68
ManufacturerAnalog Devices
ADSP2115KP80 datasheet
 


Specifications of ADSP2115KP80

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ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
INTERRUPTS & FLAGS
Parameter
Timing Requirement:
1
t
IRQx
or FI Setup before CLKOUT Low
IFS
1
t
IRQx
or FI Hold after CLKOUT High
IFH
Switching Characteristic:
t
FO Hold after CLKOUT High
FOH
t
FO Delay from CLKOUT High
FOD
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t
and t
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
IFS
IFH
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
FLAG
OUTPUT(S)
IRQx
10.24 MHz
Min
Max
2, 3
44.4
2, 3
24.4
0
15
t
FOD
t
FOH
t
IFH
FI
t
IFS
Figure 40. Interrupts & Flags
–46–
Frequency
Dependency
Min
Max
Unit
0.25t
+ 20
ns
CK
0.25t
ns
CK
ns
ns
REV. B