ADSP2115KP80

Manufacturer Part NumberADSP2115KP80
DescriptionPLCC-68
ManufacturerAnalog Devices
ADSP2115KP80 datasheet
 


Specifications of ADSP2115KP80

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Page 48/64

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ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
MEMORY READ
Parameter
Timing Requirement:
t
RD Low to Data Valid
RDD
t
A0–A13, PMS, DMS, BMS to Data Valid
AA
t
Data Hold from RD High
RDH
Switching Characteristic:
t
RD Pulse Width
RP
t
CLKOUT High to RD Low
CRD
t
A0–A13, PMS, DMS, BMS Setup before RD Low
ASR
t
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
RDA
t
RD High to RD or WR Low
RWR
w = wait states
t
CK.
CLKOUT
A0 – A13
DMS, PMS
BMS
RD
D
WR
Frequency
10.24 MHz
Dependency
Min
Max
Min
33.8
49.2
0
43.8
0.5t
19.4
34.4
0.25t
12.4
0.25t
14.4
0.25t
38.8
0.5t
t
RDA
t
t
ASR
RP
t
CRD
t
RDD
t
AA
Figure 42. Memory Read
–48–
Max
Unit
0.5t
– 15 + w
ns
CK
0.75t
– 24 + w
ns
CK
ns
– 5 + w
ns
CK
– 5
0.25t
+ 10
ns
CK
CK
– 12
ns
CK
– 10
ns
CK
– 10
ns
CK
t
RWR
t
RDH
REV. B