ADSP21160MKBZ80 Analog Devices, ADSP21160MKBZ80 Datasheet

ADSP21160MKBZ80

Manufacturer Part Number

ADSP21160MKBZ80

Description

BGA

Manufacturer

Analog Devices

Datasheet

1.ADSP21160NCB100.pdf (52 pages)

Specifications of ADSP21160MKBZ80

Date_code

07+

Current page: 1 of 52
Download datasheet (735Kb)

SHARC is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

SUMMARY

High-Performance 32-Bit DSP—Applications in Audio,

Super Harvard Architecture—Four Independent Buses

Backwards-Compatible—Assembly Source Level

Single-Instruction-Multiple-Data (SIMD) Computational

Integrated Peripherals—Integrated I/O Processor,

Medical, Military, Graphics, Imaging, and

Communication

for Dual Data Fetch, Instruction Fetch, and

Nonintrusive, Zero-Overhead I/O

Compatible with Code for ADSP-2106x DSPs

Architecture—Two 32-Bit IEEE Floating-Point

Computation Units, Each with a Multiplier, ALU,

Shifter, and Register File

4 M Bit On-Chip Dual-Ported SRAM, Glueless

Multiprocessing Features, and Ports (Serial, Link,

External Bus, and JTAG)

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One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700

Fax:781/326-8703

KEY FEATURES

80 MHz (12.5 ns) Core Instruction Rate

Single-Cycle Instruction Execution, Including SIMD

480 MFLOPS Peak and 320 MFLOPS Sustained

Dual Data Address Generators (DAGs) with Modulo and

Zero-Overhead Looping and Single-Cycle Loop Setup,

IEEE 1149.1 JTAG Standard Test Access Port and

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Operations in Both Computational Units

Performance (Based on FIR)

Bit-Reverse Addressing

Providing Efficient Program Sequencing

On-Chip Emulation

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