ADSP21161NCCAZ100

Manufacturer Part NumberADSP21161NCCAZ100
DescriptionQFP
ManufacturerAnalog Devices
ADSP21161NCCAZ100 datasheet
 

Specifications of ADSP21161NCCAZ100

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SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Wireless Communications,
Graphics, Imaging, Motor-Control, and Telephony
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Code Compatible with All Other SHARC Family DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
2
Serial Ports Offer I
S Support Via 8 Programmable and
Simultaneous Receive or Transmit Pins, which
Support up to 16 Transmit or 16 Receive Channels of
Audio
CORE PROCESSOR
INSTRUCTION
TIMER
DAG1
DAG2
PROGRAM
8
4
32
8
4
32
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
BUS
PM DATA BUS
CONNECT
(PX)
DM DATA BUS
DATA
REGISTER
FILE
(PEX)
BARREL
16
40-BIT
SHIFTER
MULT
ALU
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Integrated Peripherals—Integrated I/O Processor,
1M Bit On-Chip Dual-Ported SRAM, SDRAM
Controller, Glueless Multiprocessing Features, and
I/O Ports (Serial, Link, External Bus, SPI, and JTAG)
ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and
40-Bit Floating-Point Formats
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
600 MFLOPs Peak and 400 MFLOPs Sustained
Performance
225-Ball 17 mm
FUNCTIONAL BLOCK DIAGRAM
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
CACHE
32
48-BIT
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
32
32
64
64
DATA
REGISTER
FILE
(PEY)
BARREL
16
40-BIT
SHIFTER
ALU
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
S
DSP Microcomputer
ADSP-21161N
17 mm MBGA Package
JTAG TEST
AND EMULATION
I/O PORT
GPIO
DATA
ADDR
FLAGS
DATA
ADDR
SDRAM
CONTROLLER
IOD
IOA
EXTERNAL PORT
64
18
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
HOST PORT
MULT
DMA
IOP
CONTROLLER
REGISTERS
(MEMORY MAPPED)
SERIAL PORTS (4)
CONTROL,
LINK PORTS (2)
STATUS, &
DATA BUFFERS
SPI PORTS (1)
I/O PROCESSOR
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
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