AT90LS85354AI ATMEL Corporation, AT90LS85354AI Datasheet

AT90LS85354AI

Manufacturer Part Number

AT90LS85354AI

Description

TQFP-44

Manufacturer

ATMEL Corporation

Datasheet

1.AT90LS85354AI.pdf (4 pages)

Specifications of AT90LS85354AI

Date_code

08+

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Errata (All Date Codes)

•

Errata (Date Codes Before 9836)

•

16. Releasing Reset Condition without Clock

15. Incorrect Channel Changes in Free Running Mode

14. 32 kHz Oscillator May Fail at Higher Voltages

Releasing Reset Condition without Clock

Incorrect Channels Change in Free Running Mode

32 kHz Oscillator May Fail at Higher Voltages

Incorrect Start-up Time

Lock Bits at High V

Error in Half Carry Flag

Error in Writing Reset Status Bits

Wake-up from Sleep Executes Instructions before the Interrupt is Serviced

The SPI Can Send Wrong Byte

Output Compare Output Value Corrupted by Writing to Port

Serial Programming at Voltages below 3.0V

Wake-up from Power-save without Global Interrupt Enabled

UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled

High Current Consumption at High V

Leakage Current on Tri-stated I/O Pins

32 kHz Oscillator

If an external reset or a watchdog reset occurs while the clock is stopped and

reset is released before the clock is restarted, the internal reset will time-out after

the start-up delay which is independent of the external clock. If no external clock

pulses are present in the period when internal reset is active, the reset does cor-

rectly cause tri-stating of the I/O while the reset is held. However, if the internal

reset is released before the clock starts running, the part does not clear I/O regis-

ters, nor set PC to 0x00. Here, stopping the clock refers to gating the external

clock input. Power-down or Power-save modes do not have this issue.

Problem Fix/Workaround

Make sure the clock is running whenever an external reset can be expected. If the

Watchdog is used, never stop an external clock.

If the ADC operates in Free Running Mode and channels are changed by writing

to ADMUX shortly after the ADC Interrupt Flag (ADIF in ADCSR) is set, the new

setting in ADMUX may affect the ongoing conversion.

Problem Fix/Workaround

Use Single Conversion Mode when scanning channels, or avoid changing

ADMUX until at least 0.5 ADC clock cycles after ADIF goes high.

When using an external 32 kHz crystal as asynchronous clock source for Timer2,

the timer may fail at voltages above 4.0V.

Problem Fix/Workaround

Keep the supply voltage below 4.0V when clocking Timer2 from an external

crystal.

and Temperature

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

AT90S/LS8535

Rev. D

Errata Sheet

Rev. 1196E–09/01

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