AT91SAM7X256AU ATMEL Corporation, AT91SAM7X256AU Datasheet

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AT91SAM7X256AU

Manufacturer Part Number
AT91SAM7X256AU
Description
QFP
Manufacturer
ATMEL Corporation
Datasheet

Specifications of AT91SAM7X256AU

Date_code
09+

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Features
Incorporates the ARM7TDMI
Internal High-speed Flash
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
Memory Controller (MC)
Reset Controller (RSTC)
Clock Generator (CKGR)
Power Management Controller (PMC)
Advanced Interrupt Controller (AIC)
Debug Unit (DBGU)
Periodic Interval Timer (PIT)
Windowed Watchdog (WDT)
Real-time Timer (RTT)
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– EmbeddedICE
– 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of
– 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (AT91SAM7X512)
– 64 Kbytes (AT91SAM7X256)
– 32 Kbytes (AT91SAM7X128)
– Embedded Flash Controller, Abort Status and Misalignment Detection
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
– Provides External Reset Signal Shaping and Reset Source Status
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
– Four Programmable External Clock Signals
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
– 2-wire UART and Support for Debug Communication Channel interrupt,
– 20-bit Programmable Counter plus 12-bit Interval Counter
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
256 Bytes (Dual Plane)
Detector
Idle Mode
Protected
Programmable ICE Access Prevention
– Leader in MIPS/Watt
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase,
– 10,000 Write Cycles, 10-year Data Retention Capability,
– Fast Flash Programming Interface for High Volume Production
Full Erase Time: 15 ms
Sector Lock Capabilities, Flash Security Bit
In-circuit Emulation, Debug Communication Channel Support
®
ARM
®
Thumb
®
Processor
AT91 ARM
Thumb-based
Microcontrollers
AT91SAM7X512
AT91SAM7X256
AT91SAM7X128
Summary
Preliminary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6120DS–ATARM–03-Oct-06

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