ATF1502AS10JI44 ATMEL Corporation, ATF1502AS10JI44 Datasheet
ATF1502AS10JI44
Manufacturer Part Number
ATF1502AS10JI44
Description
PLCC44
Manufacturer
ATMEL Corporation
Datasheet
1.ATF1502AS10AC44.pdf
(26 pages)
Specifications of ATF1502AS10JI44
Date_code
04+
Features
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Enhanced Features
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High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
Advanced Power Management Features
Automatic 10 µA Standby for “L” Version
Pin-controlled 1 mA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and TQFP
Advanced EEPROM Technology
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-fee/RoHS Compliant) Package Options
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
(“L” Versions)
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
CC
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
– Input Transition Detection
– Power-down (“L” Versions)
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Power-up Reset Option
High-
performance
EEPROM CPLD
ATF1502AS
ATF1502ASL
Rev. 0995K–PLD–6/05
1
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