ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Clear Timer on Compare
Match (CTC) Mode
ATmega8515(L)
110
In clear timer on compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Reg-
ister are used to manipulate the counter resolution. In CTC mode the counter is cleared
to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or
the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter,
hence also its resolution. This mode allows greater control of the Compare Match output
frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 52. The counter value
(TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then
counter (TCNT1) is cleared.
Figure 52. CTC Mode, Timing Diagram
TCNTn
OCnA
(Toggle)
Period
1
An interrupt can be generated at each time the counter value reaches the TOP value by
either using the OCF1A or ICF1 Flag according to the register used to define the TOP
value. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing the TOP to a value close to BOTTOM when the
counter is running with none or a low prescaler value must be done with care since the
CTC mode does not have the double buffering feature. If the new value written to
OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the
Compare Match. The counter will then have to count to its maximum value (0xFFFF)
and wrap around starting at 0x0000 before the Compare Match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double
buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle
its logical level on each Compare Match by setting the Compare Output mode bits to
toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless
the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated
will have a maximum frequency of f
The waveform frequency is defined by the following equation:
f
OCnA
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV1 Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x0000.
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnA1:0 = 1)
2
3
4
= f
/2 when OCR1A is set to zero (0x0000).
OC
A
clk_I/O
1
f
clk_I/O
=
-------------------------------------------------- -
(
)
2 N
1
+
OCRnA
2512J–AVR–10/06