ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Page 126/257

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Serial Peripheral
Interface – SPI
ATmega8515(L)
126
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega8515 and peripheral devices or between several AVR devices.
The ATmega8515 SPI includes the following features:
Full Duplex, 3-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
(1)
Figure 60. SPI Block Diagram
DIVIDER
/2/4/8/16/32/64/128
Note:
1. Refer to Figure 1 on page 2, and Table 29 on page 67 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 61.
The system consists of two Shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective Shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
change data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After
each data packet, the Master will synchronize the Slave by pulling high the Slave Select,
SS, line.
2512J–AVR–10/06