ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Page 182/257

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Parallel Programming
Parameters, Pin
Mapping, and
Commands
Signal Names
ATmega8515(L)
182
This section describes how to parallel program and verify Flash Program memory,
EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8515. Pulses
are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATmega8515 are referenced by signal names describ-
ing their functionality during parallel programming, see Figure 75 and Table 85. Pins not
described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-
tive pulse. The bit coding is shown in Table 87.
When pulsing WR or OE, the command loaded determines the action executed. The dif-
ferent Commands are shown in Table 88.
Figure 75. Parallel Programming
RDY/BSY
OE
WR
BS1
XA0
XA1
PAGEL
+12 V
BS2
Table 85. Pin Name Mapping
Signal Name in Programming Mode
RDY/BSY
OE
WR
BS1
XA0
XA1
PAGEL
BS2
DATA
+5V
PD1
VCC
PD2
PB7 - PB0
DATA
PD3
PD4
PD5
PD6
PD7
RESET
PA0
XTAL1
GND
Pin Name
I/O
Function
0: Device is busy programming, 1:
PD1
O
Device is ready for new command
PD2
I
Output Enable (Active low)
PD3
I
Write Pulse (Active low)
Byte Select 1 (“0” selects low
PD4
I
byte, “1” selects high byte)
PD5
I
XTAL Action Bit 0
PD6
I
XTAL Action Bit 1
Program memory and EEPROM
PD7
I
data Page Load
Byte Select 2 (“0” selects low
PA0
I
byte, “1” selects 2’nd high byte)
Bi-directional Data bus (Output
PB7-0
I/O
when OE is low)
2512J–AVR–10/06