ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Page 60/257

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Ports as General Digital
I/O
Configuring the Pin
ATmega8515(L)
60
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a
functional description of one I/O-port pin, here generically called Pxn.
(1)
Figure 30. General Digital I/O
Pxn
PUD:
PULLUP DISABLE
SLEEP:
SLEEP CONTROL
clk
:
I/O CLOCK
I/O
Note:
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O Ports” on page 75, the DDxn bits are accessed at the DDRx
I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx
I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-
ured as an input pin.
If PORTxn is written a logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written a logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when a
reset condition becomes active, even if no clocks are running.
If PORTxn is written a logic one when the pin is configured as an output pin, the port pin
is driven high (one). If PORTxn is written a logic zero when the pin is configured as an
output pin, the port pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
Q
D
DDxn
Q
CLR
RESET
Q
D
PORTxn
Q
CLR
RESET
SLEEP
SYNCHRONIZER
D
Q
D
Q
PINxn
L
Q
Q
WDx:
WRITE DDRx
RDx:
READ DDRx
WPx:
WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
PUD
WDx
RDx
WPx
RRx
RPx
clk
I/O
,
I/O
2512J–AVR–10/06