ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Reading the Pin Value
2512J–AVR–10/06
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 24 summarizes the control signals for the pin value.
Table 24. Port Pin Configurations
PUD
DDxn
PORTxn
(in SFIOR)
0
0
X
0
1
0
0
1
1
1
0
X
Output
1
1
X
Output
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
31 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
respectively.
Figure 31. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIONS
XXX
SYNC LATCH
PINxn
r17
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the suc-
ceeding positive clock edge. As indicated by the two arrows t
ATmega8515(L)
I/O
Pull-up
Comment
Input
No
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
Input
Yes
low.
Input
No
Tri-state (Hi-Z)
No
Output Low (Sink)
No
Output High (Source)
XXX
in r17, PINx
0x00
t
pd, max
t
pd, min
pd,max
and t
pd,max
pd,min
0xFF
and t
, a single
pd,min
61