ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Page 62/257

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ATmega8515(L)
62
signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 32. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay t
clock period.
Figure 32. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
out PORTx, r16
SYNC LATCH
PINxn
r17
through the synchronizer is one system
pd
0xFF
nop
in r17, PINx
0x00
0xFF
t
pd
2512J–AVR–10/06