ATMEGA8515L8AU

Manufacturer Part NumberATMEGA8515L8AU
DescriptionTQFP44
ManufacturerATMEL Corporation
ATMEGA8515L8AU datasheet
 

Specifications of ATMEGA8515L8AU

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Unconnected pins
Alternate Port Functions
ATmega8515(L)
64
If some pins are unused, it is recommended to ensure that these pins have a defined
level. Even though most of the digital inputs are disabled in the deep sleep modes as
described above, floating inputs should be avoided to reduce current consumption in all
other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal
pull-up. In this case, the pull-up will be disabled during reset. If low power consumption
during reset is important, it is recommended to use an external pull-up or pull-down.
Connecting unused pins directly to V
cause excessive currents if the pin is accidentally configured as an output.
Most port pins have alternate functions in addition to being general digital I/Os. Figure
33 shows how the port pin control signals from the simplified Figure 30 can be overrid-
den by alternate functions. The overriding signals may not be present in all port pins, but
the figure serves as a generic description applicable to all port pins in the AVR micro-
controller family.
Figure 33. Alternate Port Functions
1
0
1
0
1
Pxn
0
1
0
PUOExn:
Pxn PULL-UP OVERRIDE ENABLE
PUOVxn:
Pxn PULL-UP OVERRIDE VALUE
DDOExn:
Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn:
Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn:
Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn:
Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
SLEEP CONTROL
Note:
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
or GND is not recommended, since this may
CC
(1)
PUOExn
PUOVxn
PUD
DDOExn
DDOVxn
Q
D
DDxn
Q
CLR
WDx
PVOExn
RESET
PVOVxn
RDx
Q
D
PORTxn
Q
DIEOExn
CLR
WPx
DIEOVxn
RESET
RRx
SLEEP
SYNCHRONIZER
RPx
SET
D
Q
D
Q
PINxn
L
Q
Q
CLR
CLR
clk
DIxn
AIOxn
PUD:
PULLUP DISABLE
WDx:
WRITE DDRx
RDx:
READ DDRx
RRx:
READ PORTx REGISTER
WPx:
WRITE PORTx
RPx:
READ PORTx PIN
clk
:
I/O CLOCK
I/O
DIxn:
DIGITAL INPUT PIN n ON PORTx
AIOxn:
ANALOG INPUT/OUTPUT PIN n ON PORTx
I/O
,
I/O
2512J–AVR–10/06