CY62167DV30LL55BVI Cypress Semiconductor Corporation., CY62167DV30LL55BVI Datasheet

CY62167DV30LL55BVI

Manufacturer Part Number

CY62167DV30LL55BVI

Description

BGA

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY62167DV30LL55BVI.pdf (12 pages)

Specifications of CY62167DV30LL55BVI

Date_code

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Cypress Semiconductor Corporation

Document #: 38-05328 Rev. *G

Features

Functional Description

The CY62167DV30 is a high-performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL

portable applications such as cellular telephones. The device

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

• TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM

• Very high speed: 45 ns

• Wide voltage range: 2.2V – 3.6V

• Ultra-low active power

• Ultra-low standby power

• Easy memory expansion with CE

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Available in Pb-free and non Pb-free 48-ball VFBGA

— Typical active current: 2 mA @ f = 1 MHz

— Typical active current: 18.5 mA @ f = f

and 48-pin TSOP I package

speed)

[1]

Power-Down

Circuit

COLUMN DECODER

DATA IN DRIVERS

, CE

1M × 16 / 2M x 8

RAM Array

•

and OE features

Max

198 Champion Court

(45 ns

) in

also has an automatic power-down feature that significantly

reduces power consumption by 99% when addresses are not

toggling. The device can also be put into standby mode when

deselected (CE

HIGH). The input/output pins (I/O

in a high-impedance state when: deselected (CE

LOW), outputs are disabled (OE HIGH), both Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

or during a Write operation (CE

LOW).

Writing to the device is accomplished by taking Chip Enables

(CE

If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O

through I/O

address pins (A

LOW, then data from I/O pins (I/O

the location specified on the address pins (A

Reading from the device is accomplished by taking Chip

Enables (CE

LOW while forcing the Write Enable (WE) HIGH. If Byte Low

Enable (BLE) is LOW, then data from the memory location

specified by the address pins will appear on I/O

High Enable (BHE) is LOW, then data from memory will appear

on I/O

sheet for a complete description of Read and Write modes.

BHE

BLE

16-Mbit (1M x 16) Static RAM

LOW and CE

•

to I/O

San Jose

), is written into the location specified on the

LOW and CE

. See the truth table at the back of this data

HIGH or CE

through A

HIGH) and Write Enable (WE) input LOW.

I/O

CA 95134-1709

BLE

BYTE

BHE

CY62167DV30 MoBL

–I/O

HIGH) and Output Enable (OE)

). If Byte High Enable (BHE) is

LOW or both BHE and BLE are

Revised July 27, 2006

through I/O

LOW, CE

through I/O

•

through A

HIGH and WE

) is written into

408-943-2600

to I/O

HIGH or CE

) are placed

. If Byte

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