CY7C1021DV3310VXI Cypress Semiconductor Corporation., CY7C1021DV3310VXI Datasheet

CY7C1021DV3310VXI

Manufacturer Part Number

CY7C1021DV3310VXI

Description

SOJ44

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1021DV3310VXI.pdf (11 pages)

Specifications of CY7C1021DV3310VXI

Date_code

05+

Current page: 1 of 11
Download datasheet (364Kb)

Cypress Semiconductor Corporation

Document #: 38-05460 Rev. *D

Features

Note

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com

• Temperature Ranges

• Pin-and function-compatible with CY7C1021CV33

• High speed

• Low active power

• Low CMOS standby power

• 2.0V data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Independent control of upper and lower bits

• Available in Pb-free 44-pin 400-Mil wide Molded SOJ,

Logic Block Diagram

— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C

— Automotive-E: –40°C to 125°C

— t

— I

44-pin TSOP II and 48-ball VFBGA packages

SB2

= 10 ns

= 60 mA @ 10 ns

= 3 mA

DATA IN DRIVERS

•

COLUMN DECODER

RAM Array

64K x 16

198 Champion Court

Functional Description

The CY7C1021DV33 is a high-performance CMOS static

RAM organized as 65,536 words by 16 bits. This device has

an automatic power-down feature that significantly reduces

power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O

written into the location specified on the address pins (A

through A

from I/O pins (I/O

specified on the address pins (A

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O

LOW, then data from memory will appear on I/O

the truth table at the end of this data sheet for a complete

description of Read and Write modes.

The input/output pins (I/O

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil

wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA

packages.

1-Mbit (64K x 16) Static RAM

•

San Jose

). If Byte High Enable (BHE) is LOW, then data

through I/O

CA 95134-1709

to I/O

I/O

through I/O

[1]

BHE

BLE

. If Byte High Enable (BHE) is

–I/O

) is written into the location

Revised November 8, 2006

through A

CY7C1021DV33

•

) are placed in a

through I/O

408-943-2600

to I/O

. See

), is

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