CY7C1041CV3320ZC Cypress Semiconductor Corporation., CY7C1041CV3320ZC Datasheet

CY7C1041CV3320ZC

Manufacturer Part Number

CY7C1041CV3320ZC

Description

TSOP

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1041CV3312ZXC.pdf (12 pages)

Specifications of CY7C1041CV3320ZC

Date_code

03+

Current page: 1 of 12
Download datasheet (585Kb)

Cypress Semiconductor Corporation

Document #: 38-05134 Rev. *H

Features

Notes:

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.

• Pin equivalent to CY7C1041BV33

• Temperature Ranges

• High speed

• Low active power

• 2.0V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• Available in Pb-free and non Pb-free 44-pin 400-mil-

Logic Block Diagram

— Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C

— Automotive-E: –40°C to 125°C

— t

— 324 mW (max.)

SOJ, 44-pin TSOP II and 48-ball FBGA packages

= 10 ns

INPUT BUFFER

DECODER

COLUMN

256K × 16

ARRAY

•

198 Champion Court

I/O

Functional Description

The CY7C1041CV33 is a high-performance CMOS Static

RAM organized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable

(BLE) is LOW, then data from I/O pins (I/O

into the location specified on the address pins (A

HIGH Enable (BHE) is LOW, then data from I/O pins

(I/O

address pins (A

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O

LOW, then data from memory will appear on I/O

the truth table at the back of this data sheet for a complete

description of Read and Write modes.

The input/output pins (I/O

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

The CY7C1041CV33 is available in a standard 44-pin

400-mil-wide body width SOJ and 44-pin TSOP II package

with center power and ground (revolutionary) pinout, as well

as a 48-ball fine-pitch ball grid array (FBGA) package.

4-Mbit (256K x 16) Static RAM

–I/O

BHE

BLE

–I/O

•

San Jose

) is written into the location specified on the

–A

Pin Configuration

CA 95134-1709

I/O

– I/O

Top View

TSOP II

[1]

. If Byte HIGH Enable (BHE) is

SOJ/

–I/O

Revised September 1, 2006

CY7C1041CV33

) are placed in a

BHE

BLE

I/O

•

–I/O

408-943-2600

–A

to I/O

), is written

). If Byte

. See

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