CY7C1041DV3310BVXI Cypress Semiconductor Corporation., CY7C1041DV3310BVXI Datasheet

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CY7C1041DV3310BVXI

Manufacturer Part Number
CY7C1041DV3310BVXI
Description
BGA
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C1041DV3310BVXI

Date_code
10+
Features
Note
Cypress Semiconductor Corporation
Document #: 38-05473 Rev. *E
Logic Block Diagram
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, available at www.cypress.com.
Pin and function compatible with CY7C1041CV33
High speed
Low active power
Low CMOS standby power
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II packages
t
I
I
AA
CC
SB2
= 10 ns
= 90 mA at 10 ns (industrial)
= 10 mA
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
198 Champion Court
INPUT BUFFER
DECODER
COLUMN
256K × 16
Functional Description
The CY7C1041DV33
organized as 256K words by 16 bits. To write to the device, take
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte
LOW Enable (BLE) is LOW, then data from IO pins (IO
is written into the location specified on the address pins (A
A
(IO
pins (A
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
BLE is LOW, then data from the memory location specified by
the address pins appears on IO
from memory appears on IO
page 9 for a complete description of read and write modes.
The input and output pins (IO
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
17
8
). If Byte HIGH Enable (BHE) is LOW, then data from IO pins
to IO
0
to A
15
4 Mbit (256K x 16) Static RAM
) is written into the location specified on the address
San Jose
17
).
[1]
,
IO
IO
CA 95134-1709
is a high performance CMOS Static RAM
0
8
–IO
–IO
BHE
WE
CE
OE
BLE
7
15
8
0
to IO
0
to IO
to IO
CY7C1041DV33
15
7
. If BHE is LOW, then data
. See the
15
) are placed in a high
Revised July 17, 2008
Truth Table
408-943-2600
0
to IO
0
on
to
7
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