CY7C68013A100AXC Cypress Semiconductor Corporation., CY7C68013A100AXC Datasheet

CY7C68013A100AXC

Manufacturer Part Number

CY7C68013A100AXC

Description

QFP100

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C68013A56LFXC.pdf (55 pages)

Specifications of CY7C68013A100AXC

Date_code

09+

Current page: 1 of 55
Download datasheet (2Mb)

Cypress Semiconductor Corporation

Document #: 38-08032 Rev. *H

1.0

• USB 2.0–USB-IF high speed certified (TID # 40440111)

• Single-chip integrated USB 2.0 transceiver, smart SIE,

• Fit, form and function compatible with the FX2

• Ultra Low power: I

• Software: 8051 code runs from:

• 16 KBytes of on-chip Code/Data RAM

• Four programmable BULK/INTERRUPT/ISOCHRO-

• Additional programmable (BULK/INTERRUPT) 64-byte

• 8- or 16-bit external data interface

• Smart Media Standard ECC generation

• GPIF (General Programmable Interface)

and enhanced 8051 microprocessor

NOUS endpoints

endpoint

— Pin-compatible

— Object-code-compatible

— Functionally-compatible (FX2LP is a superset)

— Ideal for bus and battery powered applications

— Internal RAM, which is downloaded via USB

— Internal RAM, which is loaded from EEPROM

— External memory device (128 pin package)

— Buffering options: double, triple, and quad

— Allows direct connection to most parallel interface

— Programmable waveform descriptors and configu-

— Supports multiple Ready (RDY) inputs and Control

ration registers to define waveforms

(CTL) outputs

full- and high-speed

Features (CY7C68013A/14A/15A/16A)

Integrated

XCVR

D+

D–

FX2LP

VCC

no more than 85 mA in any mode

1.5k

connected for

full speed

Enhanced USB core

Simplifies 8051 code

XCVR

USB

24 MHz

Ext. XTAL

2.0

x20

PLL

/0.5

/1.0

/2.0

1.1/2.0

Smart

Engine

USB

•

High-performance micro

with lower-power options

using standard tools

Figure 1-1. Block Diagram

3901 North First Street

EZ-USB FX2LP™ USB Microcontroller

four clocks/cycle

Easy firmware changes

12/24/48 MHz,

8051 Core

“Soft Configuration”

16 KB

RAM

1.1

• Integrated, industry-standard enhanced 8051

• 3.3V operation with 5V tolerant inputs

• Vectored USB interrupts and GPIF/FIFO interrupts

• Separate data buffers for the Set-up and Data portions

• Integrated I

• Four integrated FIFOs

• CY7C68014A: Ideal for battery powered applications

• CY7C68013A: Ideal for non-battery powered applica-

• Available in four lead-free packages with up to 40 GPIOs

of a CONTROL transfer

tions

— 48-MHz, 24-MHz, or 12-MHz CPU operation

— Four clocks per instruction cycle

— Two USARTS

— Three counter/timers

— Expanded interrupt system

— Two data pointers

— Integrated glue logic and FIFOs lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

— Uses external clock or asynchronous strobes

— Easy interface to ASIC and DSP ICs

— Suspend current: 100 µA (typ)

— Suspend current: 300 µA (typ)

— 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),

56-pin QFN (24 GPIOs) and 56-pin SSOP (24 GPIOs)

ECC

Features (CY7C68013A/14A only)

FIFO and endpoint memory

(master or slave operation)

•

Additional I/Os (24)

C controller, runs at 100 or 400 kHz

San Jose

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

GPIF

FIFO

4 kB

Master

ADDR (9)

RDY (6)

CTL (6)

8/16

CA 95134

including two USARTS

Up to 96 MBytes/s

standards such as

programmable I/F

ATAPI, EPP, etc.

to ASIC/DSP or bus

Revised April 18, 2005

Abundant I/O

General

burst rate

•

408-943-2600

Related parts for CY7C68013A100AXC

Related keywords

CY7C68013A100AXC datasheet
CY7C68013A100AXC data sheet
CY7C68013A100AXC pdf datasheet
CY7C68013A100AXC component
CY7C68013A100AXC part
CY7C68013A100AXC distributor
CY7C68013A100AXC RoHS
CY7C68013A100AXC datasheet download