EP1K10TC1001

Manufacturer Part NumberEP1K10TC1001
DescriptionQFP100
ManufacturerAltera Corporation
EP1K10TC1001 datasheet
 

Specifications of EP1K10TC1001

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May 2003, ver. 3.4
Features...
TM
Table 1. ACEX
1K Device Features
Feature
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-ACEX-3.4
Programmable Logic Device Family
®
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic array for general logic functions
High density
10,000 to 100,000 typical gates (see
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
Cost-optimized process
Low cost solution for high-performance communications
applications
System-level features
MultiVolt
TM
I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
Low power consumption
Bidirectional I/O performance (setup time [t
output delay [t
]) up to 250 MHz
CO
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Extended temperature range
EP1K10
EP1K30
10,000
30,000
56,000
119,000
576
1,728
3
6
12,288
24,576
136
171
ACEX 1K
Data Sheet
Table
1)
] and clock-to-
SU
EP1K50
EP1K100
50,000
100,000
199,000
257,000
2,880
4,992
10
12
40,960
49,152
249
333
13
1