EP1K10TC1001 Altera Corporation, EP1K10TC1001 Datasheet

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EP1K10TC1001

Manufacturer Part Number
EP1K10TC1001
Description
QFP100
Manufacturer
Altera Corporation
Datasheet

Specifications of EP1K10TC1001

Date_code
04+
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Features...
Altera Corporation
DS-ACEX-3.4
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
May 2003, ver. 3.4
Table 1. ACEX
Feature
TM
1K Device Features
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
High density
Cost-efficient programmable architecture for high-volume
applications
System-level features
Extended temperature range
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic array for general logic functions
10,000 to 100,000 typical gates (see
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-optimized process
Low cost solution for high-performance communications
applications
MultiVolt
5.0-V devices
Low power consumption
Bidirectional I/O performance (setup time [t
output delay [t
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
EP1K10
10,000
56,000
12,288
576
136
3
®
TM
I/O pins can drive or be driven by 2.5-V, 3.3-V, or
Programmable Logic Device Family
CO
]) up to 250 MHz
119,000
EP1K30
30,000
24,576
1,728
171
6
Table
199,000
EP1K50
50,000
40,960
2,880
249
10
1)
SU
ACEX 1K
] and clock-to-
EP1K100
100,000
257,000
49,152
Data Sheet
4,992
333
12
1
13

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