EPF10K30RC2083

Manufacturer Part NumberEPF10K30RC2083
DescriptionQFP
ManufacturerAltera Corporation
EPF10K30RC2083 datasheet
 

Specifications of EPF10K30RC2083

Date_code04+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 55/128

Download datasheet (2Mb)Embed
PrevNext
Figure 23. Output Drive Characteristics for EPF10K250A Device
50
40
Typical I
O
30
Output
Current (mA)
20
10
1
V
Timing Model
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
I
OL
V
= 3.3 V
CCI NT
Typical I
V
= 3.3 V
CCI O
Output
Room Temperature
Current (mA)
I
OH
2
3
4
Output Voltage (V)
O
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
LE register clock-to-output delay (t
Interconnect delay (t
SAMEROW
LE look-up table delay (t
LE register setup time (t
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
50
40
V
CCI NT
O
V
CCI O
30
Room Temperature
20
10
I
OH
1
2
V
Output Voltage (V)
O
)
CO
)
)
LUT
)
SU
I
OL
= 3.3 V
= 2.5 V
3
4
55