EPF10K30RI2404 Altera Corporation, EPF10K30RI2404 Datasheet - Page 43

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EPF10K30RI2404

Manufacturer Part Number
EPF10K30RI2404
Description
QFP240
Manufacturer
Altera Corporation
Datasheet

Specifications of EPF10K30RI2404

Date_code
09+
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 18
shows the timing requirements for the JTAG signals.
Figure 18. JTAG Waveforms
TMS
TDI
t
JCP
t
t
JCH
JCL
TCK
t
JPZX
TDO
t
JSSU
Signal
to Be
Captured
t
JSZX
Signal
to Be
Driven
Table 16
shows the timing parameters and values for FLEX 10K devices.
Table 16. JTAG Timing Parameters & Values
Symbol
Parameter
t
TCK clock period
JCP
t
TCK clock high time
JCH
t
TCK clock low time
JCL
t
JTAG port setup time
JPSU
t
JTAG port hold time
JPH
t
JTAG port clock to output
JPCO
t
JTAG port high impedance to valid output
JPZX
t
JTAG port valid output to high impedance
JPXZ
t
Capture register setup time
JSSU
t
Capture register hold time
JSH
t
Update register clock to output
JSCO
t
Update register high-impedance to valid output
JSZX
t
Update register valid output to high impedance
JSXZ
t
t
JPH
JPSU
t
JPCO
t
JSH
t
t
JSCO
JSXZ
t
JPXZ
Min
Max
Unit
100
ns
50
ns
50
ns
20
ns
45
ns
25
ns
25
ns
25
ns
20
ns
45
ns
35
ns
35
ns
35
ns
43

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