Figure 24. FLEX 10K Device Timing Model
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Timing simulation and delay prediction are available with the
MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time analysis, and
device-wide performance analysis.
to and from the various elements of the FLEX 10K device.
shows the overall timing model, which maps the possible paths